Latchup Immunity in High Temperature Bulk CMOS Devices

Abstract

High density, low power 180nm and 130nm CMOS SRAMs have been manufactured on bulk silicon wafers using a modified CMOS commercial process that hardens the junction isolation and has demonstrated latchup immunity at temperatures >200°C. TCAD simulations confirmed by high temperature testing indicate that a latch up free performance of SRAMs manufactured on bulk silicon modified by the HardSIL™ technology will easily extrapolate to 250°C. These process modifications result in significantly more robust CMOS circuits making them more suitable for highly reliable operations in extreme environments – such as radiation and high temperature. The unique capability of HardSIL™ technology to enhance existing IC products has demonstrated excellent results with several commercial circuits. This new approach enables the conversion of commercial off the shelf (COTS) circuits to hardened hi-rel commercial circuits with dramatically improved survivability to either radiation or high temperatures. Latchup immunity has been demonstrated on two high-density bulk silicon CMOS SRAMs: a 16Mbit asynchronous SRAM manufactured at the 180nm design node and an 8Mbit dual port synchronous SRAM manufactured at 130nm. Both parts were produced in a high-volume, low-defect commercial CMOS fabrication facility in the USA. The SRAM parts were packaged in ceramic packages and characterized at temperatures ranging from 25°C to 225°C. Characterization data indicates both excellent static leakage and dynamic circuit performance for both SRAMs at these elevated temperatures. Device test structures designed with typical layout spacing rules were evaluated to quantify latchup and isolate the various leakage mechanisms. Detailed results for these test structures are presented and compared to the SRAMs using the modified HardSIL™ process.

Energy-efficient and Reliable Inference in Nonvolatile Memory under Extreme Operating Conditions

“…CMOS performance can degrade with increasing temperature due to increased leakage current, while typical CMOS devices can operate well up to 175 • C [63]. Radiation hardened bulk CMOS technology can increase this range further to 250 • C [63,83]. Hence, CMOS technology is well suited to operate within the expected temperature range of LEO satellites.…”

Enabling Bulk Silicon CMOS Technology for Integration, Reliability, and Extended Lifetime at High Temperature

“…It is a known problem that latchup becomes increasingly likely with increasing temperature, due to decreasing trigger voltage and trigger current margins and to decreasing holding voltages [1,2]. This is demonstrated on test structures designed with varying width and typical core and I/O spacings in the 130nm process (figure 1) [3]. In these sample measurements, the P + current was forced in 1mA increments to the compliance limit of the test equipment.…”