Hydrogenated amorphous silicon ͑a-Si:H͒ and Si-O-H heterogeneous thin films have been examined for their potential to photoluminesce. In this study, 50 nm a-Si:H films were deposited and oxidized to understand how film morphology affects their optical properties. Glancing angle x-ray diffraction ͑XRD͒, x-ray reflectivity, x-ray photoelectron spectroscopy, optical absorption spectroscopy in the wavelength range 250-1000 nm, and Fourier transform infrared measurements were used to complement room temperature photoluminescence ͑PL͒ studies. The results are discussed in light of the standard models for room temperature visible PL for a-SiO x :H films and silicon nanocrystals. The PL peak at 1.6 eV arises from silicon nanocrystals. Modeling this band to estimate the quantum dot size indicates that the mean silicon crystallite diameter is ϳ5 nm, while XRD analysis gives ϳ9Ϯ1 nm. The discrepancy in the estimation of crystallite size by the XRD method and PL analysis is attributed to the columnar growth of the silicon nanocrystals.
Recently we have reported the successful operation of a database filter demonstrator system implemented with 4x4 hybrid arrays of vertical cavity surface emitting lasers and heterojunction phototransistors (VCSEWHPT) configured as AND and XOR logic gates 111. This system accepts page oriented inputs potentially provided by holographic or other massively parallel optical memory. Each logic gate array of this system is composed of two chips (an HPT array and a VCSEL array) connected together with wire bonds to traces on a ceramic submount. While this hybrid based smart pixel implementation allowed for a proof-of-principal demonstration, a device technology that provides greater pixel density, higher yield, and simpler packaging, which can be fabricated by an existing foundry is desirable for the next generation database filter demonstrator. This paper presents a new smart pixel design for the data filter which combines the four chips of the previous system into a single component chip. This eliminates many of the optical components, dramaticallly reduces the size of the system, and simplifies the optical alignment. The redesigned chip is being fabricated by Vitesse through the MOSIS foundry and uses MSM photodetectors and MESFETs instead of the HPTs. The VCSELs are flip-chip bump bonded to each pixel using a coplanar bonding technique similar to that developed by Goossen, et. a1.[2] for the SEED devices. The paper will describe the pixel design and measured characteristics.The 8 x 8 pixel array is monolithically integrated on a single 2 . 5 m x 2.5" integrated circuit. A pixel and array layout are shown in figure 1. The pixel is made up of 3-50pm X 50pm MSM photodetectors, 2-input AND and XOR gates made up of enhancement mode MESFETs with depletion mode MESFETs as active loads, a 4 stage current step-up (width of 12pm to 360pm for a 15mA max current) to drive the VCSEL, and the VCSEL bonding pads with dimensions of 40pm X c 125 Figurel: PixdandSxSarrayofpixels laycut 1 03
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