Timepix4 is a 24.7 × 30.0 mm2 hybrid pixel detector readout ASIC which has been designed to permit detector tiling on 4 sides. It consists of 448 × 512 pixels which can be bump bonded to a sensor with square pixels at a pitch of 55 µm. Like its predecessor, Timepix3, it can operate in data driven mode sending out information (Time of Arrival, ToA and Time over Threshold, ToT) only when a pixel has a hit above a pre-defined and programmable threshold. In this mode hits can be tagged to a time bin of <200 ps and Timepix4 can record hits correctly at incoming rates of ∼3.6 MHz/mm2/s. In photon counting (or frame-based) mode it can count incoming hits at rates of up to 5 GHz/mm2/s. In both modes data is output via between 2 and 16 serializers each running at a programmable data bandwidth of between 40 Mbps and 10 Gbps. The specifications, architecture and circuit implementation are described along with first electrical measurements and measurements with radioactive sources. In photon counting mode X-ray images have been taken at a threshold of 650 e− (with <10 masked pixels). In data driven mode images were taken of ToA/ToT data using a 90Sr source at a threshold of 800 e− (with ∼120 masked pixels).

Silicon detectors based on the HV-CMOS technology are being investigated as possible candidate for the outer layers of the ATLAS pixel detector for the High Luminosity LHC. In this framework the H35Demo ASIC has been produced in the 350 nm AMS technology (H35). The H35Demo chip has a large area (18.49 × 24.40 mm 2 ) and includes four different pixel matrices and three test structures. In this paper the radiation hardness properties, in particular the evolution of the depletion region with fluence is studied using edge-TCT on test structures. Measurements on the test structures from chips with different substrate resistivity are shown for non irradiated and irradiated devices up to a cumulative fluence of 2 · 10 15 1 MeV n eq /cm 2 .

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HV-CMOS sensors can offer important advantages for large area tracking systems in high energy physics experiments. Their use in future collider experiments (HL-LHC) will depend on the capacity to sustain the anticipated radiation levels. This contribution presents the design and preliminary measurements of an HV-CMOS pixel demonstrator in the ams 0.35 µm HV-CMOS technology for the ATLAS upgrade. The readout is compatible with the FEI4 ASIC. To increase the depletion region, wafers with moderate/high resistivities have been used. Various alternatives are implemented with different gain, speed, number of readout stages and output type.