The Timepix3, hybrid pixel detector (HPD) readout chip, a successor to the Timepix [1] chip, can record time-of-arrival (ToA) and time-over-threshold (ToT) simultaneously in each pixel. ToA information is recorded in a 14-bit register at 40 MHz and can be refined by a further 4 bits with a nominal resolution of 1.5625 ns (640 MHz). ToT is recorded in a 10-bit overflow controlled counter at 40 MHz. Pixels can be programmed to record 14 bits of integral ToT and 10 bits of event counting, both at 40 MHz. The chip is designed in 130 nm CMOS and contains 256 × 256 pixel channels (55 × 55 µm 2 ). The chip, which has more than 170 M transistors, has been conceived as a general-purpose readout chip for HPDs used in a wide range of applications. Common requirements of these applications are operation without a trigger signal, and sparse readout where only pixels containing event information are read out.A new architecture has been designed for sparse readout and can achieve a throughput of up to 40 Mhits/s/cm 2 . The flexible architecture offers readout schemes ranging from serial (one link) readout (40 Mbps) to faster parallel (up to 8 links) readout of 5.12 Gbps. In the ToA/ToT operation

The Medipix2 chip is a pixel-detector readout chip consisting of 256 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. Each pixel cell contains around 500 transistors and occupies a total surface area of 55 m 55 m. A 20-m wide octagonal opening connects the detector and the preamplifier input via bump bonding. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to create a pulse if the preamplifier output falls within a defined energy window. These digital pulses are then counted with a 13-b pseudorandom counter. The counter logic, based in a shift register, also behaves as the input-output register for the pixel. Each cell also has an 8-b configuration register which allows masking, test-enabling and 3-b individual threshold adjust for each discriminator. The chip can be configured in serial mode and readout either serially or in parallel. The chip is designed and manufactured in a 6-metal 0.25m CMOS technology. First measurements show an electronic pixel noise of 140 e root mean square (rms) and an unadjusted threshold variation around 360 e rms.

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The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. Each pixel cell contains around 500 transistors and occupies a total surface area of 55 Pm x 55 Pm. A 20 Pm width octagonal opening connects the detector and the preamplifier input via bump-bonding. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to create a pulse if the preamplifier output falls within a defined energy window. These digital pulses are then counted with a 13-bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each cell also has an 8-bit configuration register which allows masking, test-enabling and 3-bit individual threshold adjust for each discriminator. The chip can be configured in serial mode and read out either serially or in parallel. The chip is designed and manufactured in a 6-metal 0.25 Pm CMOS technology. Preliminary measurements show very good agreement with simulations. 1484 0-7803-7324-3/02/$17.00 © 2002 IEEE