For the first time, high power 4H-SiC n-IGBTs have been demonstrated with 13 kV blocking and a low Rdiff,on of 22 mWcm2 which surpasses the 4H-SiC material limit for unipolar devices. Normally-off operation and >10 kV blocking is maintained up to 200oC base plate temperature. The on-state resistance has a slight positive temperature coefficient which makes the n-IGBT attractive for parallel configurations. MOS characterization reveals a low net positive fixed charge density in the oxide and a low interface trap density near the conduction band which produces a 3 V threshold and a peak channel mobility of 18 cm2/Vs in the lateral MOSFET test structure. Finally, encouraging device yields of 64% in the on-state and 27% in the blocking indicate that the 4H-SiC n-IGBT may eventually become a viable power device technology.

Basal plane dislocations (BPDs) introduced into SiC epitaxial layers, 25 μm thick, by the combination of implantation and activation anneal are directly observed by ultraviolet photoluminescence (UVPL) imaging. BPD loops appear to originate at micron-sized or smaller areas at the surface. These loops expand by gliding along the basal plane in the offcut direction until the loops approach the substrate. The loops can glide perpendicular to the offcut direction by many millimeters.

Significant advancement has been made in the gate oxide reliability of SiC MOS devices to enable the commercial release of Cree’s Z-FET™ product. This paper discusses the key reliability results from Time-Dependent-Dielectric-Breakdown (TDDB) and High Temperature Gate Bias (HTGB) measurements that indicate that the SiC MOSFETs can demonstrate excellent lifetime and stable operation in the field.

DC characteristics of 4H-SiC p-channel IGBTs capable of blocking -12 kV and conducting -0.4 A (-100 A/cm2) at a forward voltage of -5.2 V at 25°C are demonstrated for the first time. A record low differential on-resistance of 14 mW×cm2 was achieved with a gate bias of -20 V indicating a strong conductivity modulation in the p-type drift region. A moderately doped current enhancement layer grown on the lightly doped drift layer effectively reduces the JFET resistance while maintains a high carrier lifetime for conductivity modulation. A hole MOS channel mobility of 12.5 cm2/V-s at -20 V of gate bias was measured with a MOS threshold voltage of -5.8 V. The blocking voltage of -12 kV was achieved by Junction Termination Extension (JTE).

DC characteristics and reverse recovery performance of 4H-SiC Junction Barrier Schottky (JBS) diodes capable of blocking in excess of 10 kV with forward conduction of 20 A at a forward voltage of less than 4 V are described. Performance comparisons are made to a similarly rated 10 kV 4H-SiC PiN diode. The JBS diodes show a significant improvement in reverse recovery stored charge as compared to PiN diodes, showing half of the stored charge at 25°C and a quarter of the stored charge at 125°C when switched to 3 kV blocking. These large area JBS diodes were also employed to demonstrate the tremendous advances that have recently been made in 4H-SiC substrate quality.