Background:
The rapid improvement in technology enables design of high-speed devices,
with development of modified computational elements for FPGA implementation. With complexity
increasing day-to-day, there is demand for modified VLSI computational elements. Basically, for the
past decade an improvement in basic VLSI Operators like Adder, multiplier is significant. The basic
multiplication operator is been completely refined in the aspects of FPGA implementation.
Materials and Methods:
This paper presents a design of 32-bit high-speed MAC unit based on Vedic
computations. Among the many sutras of Vedic mathematics, by using the urdhvatriyagbhyam sutra
the products are generated in parallel. This proposed technique results in multiplication step reduction.
Results:
The result shows that the proposed MAC unit, the number of steps required for multiplication
and addition has been reduced, it leads to the decrease in area size. In comparison with the performance
of existing method to proposed MAC, the LUT's are reduced by 50 percent.
Conclusion:
This paper comprehensively describes the basic Multiplication operation using
urdhvatriyaghyam sutra for parallel multiplication process. Based on the Vedic sutras, the performance
was analyzed on a hardware platform Spartan-3E Xilinx FPGA Device for a 32-bit MAC
unit. The Implementation results shoes reduction in critical delay and area when compared to conventional
booth multiplier-based MAC Design. Hence this works concludes that the proposed Vedic
multiplier is suitable for constructing high speed MAC units.
Augmented reality system enables effective interaction with field view data and executes a particular task effectively by visual display aid. Precision agriculture involves precision measurement, data generation, analysis for interpretation of data, and decision-making to improve the yield and monitor the plant. Augmented reality will help to systematically acquire the needed data and interpret the required information from the analytical result on the field. This paper presents a low-cost development of the augmented reality system for on-field analysis of plant diseases. The article also presents a framework of deep learningbased cloud data analytic to enable on-field real-time interaction between the farmers and cloud data processing systems using a head-mounted unit. The proposed augmented reality system performance is validated for its accuracy in detecting plant diseases, real-time interaction response time, and ease of usage by the farmer community. The results show that the proposed mechanism will be able to produce real-time augment interaction to the farmer for the task of disease inspection of the plant effectively and accurately.
The high‐frequency circuits used in communication systems significantly depend on the functioning of the Phase‐Locked Loop (PLL). The power consumption is traded with the performance in the high‐frequency PLL. The proposed robust Phase and Frequency Detector (PFD) has multiple benefits of low‐power and reliable functioning at high frequency. The PFD highly contributes to the stable performance of the PLL, and this work proposes a 10T PFD for low‐power. The proposed PFD employs Gate Diffusion Input (GDI) logic based D‐flip flop and the pass transistor logic in the reset path to reduce power consumption. The PFD uses only 10 transistors, enabling a faster reset path and consuming less power at high frequencies. The 10T PFD was designed using 90 nm CMOS PDKs and simulated using CADENCE Specter for functional verification and performance analysis. The 10T PFD achieved a reset time of 61.4 ps at 3 GHz alongside a power consumption of 189.2 nW. Also, the overall power consumption of PLL using the proposed PFD at 3 GHz was demonstrating the effectiveness of 10T PFD over other conventional PFDs.
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