The operating principle of resistive random access memories (RRAMs) relies on the distribution of ionic species and their influence on the electron transport. Taking into account that formation and annihilation of conducting filaments (CFs) is the driving mechanism for the switching effect, it is very important to control the regions where these filaments will evolve. Thus, homolayers of titanium oxide with different oxygen contents were fabricated in order to tune the local electrical and thermal properties of the CFs and narrow down the potential percolation paths. We show that the oxygen content in the top layer of the TiO2−x/TiO2−y bilayer memristors can directly influence the morphology of the layers which affect the diffusion barrier and consequently the diffusivity and drift velocity of oxygen vacancies, yielding in important enhancement of switching characteristics, in terms of spatial uniformity (σ/μ < 0.2), enlarged switching ratio (∼104), and synaptic learning. In order to address the experimental data, a physical model was applied, divulging the crucial role of temperature, electric potential and oxygen vacancy density on the switching effect and offering physical insights to the SET/RESET transitions and the analog switching. The forming free nature of all the devices in conjunction with the self-rectifying behavior, should also be regarded as important assets towards RRAM device optimization.

Although multilevel capability is probably the most important property of resistive random access memory (RRAM) technology, it is vulnerable to reliability issues due to the stochastic nature of conducting filament (CF) creation. As a result, the various resistance states cannot be clearly distinguished, which leads to memory capacity failure. In this work, due to the gradual resistance switching pattern of TiO2−x-based RRAM devices, we demonstrate at least six resistance states with distinct memory margin and promising temporal variability. It is shown that the formation of small CFs with high density of oxygen vacancies enhances the uniformity of the switching characteristics in spite of the random nature of the switching effect. Insight into the origin of the gradual resistance modulation mechanisms is gained by the application of a trap-assisted-tunneling model together with numerical simulations of the filament formation physical processes.

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Abstract-In this paper we present a FinFET focused variability-aware compact model extraction and generation technology supporting design-technology co-optimization (DTCO). 14-nm CMOS technology generation SOI FinFETs are used as test-bed transistors to illustrate our approach. The TCAD simulations include long-range process-induced variability using a design of experiment (DoE) approach and short-range purely statistical variability (

In this paper we present a comprehensive computational study of silicon nanowire transistor (SNT) and a SNM SRAM cell based on advanced design technology cooptimization (DTCO) TCAD tools. Utilizing this methodology, we provide guidelines and solutions for 5 nm and beyond in CMOS technology. At first, drift-diffusion (DD) results are fully calibrated against a PoissonSchrodinger (PS) solution to calibrate density-gradient quantum corrections, and ensemble Monte Carlo (EMC) simulations to calibrate transport models. The calibrated DD gives us the capability to simulate statistical variability in nanowire transistors of the 5nm node and beyond accurately and efficiently. Various SNT structures are evaluated in terms of device figures of merit, and optimization of SNTs in terms of electrostatics driven performance is carried out. A variability-aware hierarchical compact model approach for SNT is adopted and used for statistical SRAM simulation near the "scaling limit". The scaling of SNTs beyond the 5 nm is also discussed.