In this study, Si implantation was used to improve the interface properties of SiC/SiO2 in 4H-SiC lateral MOSFETs. In lateral n-channel MOSFETs, a 4%–6% improvement on the linear and saturation current was observed with Si implantation. From high/low-frequency CV measurements, the Si-implanted n-type MOS capacitor showed a 20% lower interface state density than the non-implanted ones at an energy level of EC − E = 0.2 eV, without degrading oxide integrity. Lateral p-channel MOSFETs, on the other hand, showed a 36.5% reduction in the linear current and a 16.6% reduction in the saturation current with Si implantation. Furthermore, the temperature coefficients of lateral and vertical MOSFETs implanted by Si were monitored up to 175 °C. The temperature coefficients of the Si-implanted n-channel and p-channel lateral MOSFETs were nearly identical to those of their non-implanted counterparts.
The MOSFET backscattering theory relies on a socalled "k B T " layer. In this letter, we adopt two different approaches to examine the temperature dependencies of the width spanned by this critical zone. First of all, a 55-nm channel length n-MOSFET is extensively characterized at three temperatures of 233 K, 263 K, and 298 K while undergoing a parameter decoupling/transformation process. A unique relationship is straightforwardly created and is comparable with that in the literature: The width of the "k B T " layer is proportional to the square root of temperature. The case of 77 K is also projected. Other corroborating evidence is a Monte Carlo particle simulation conducted on an 80-nm-long silicon conductor with the "k B T " layer's width proportional to the temperature in the high field region. Without adjusting any parameters, the backscattering theory is shown to work well for the demonstrated temperatures down to 77 K.
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