In this article, we summarize the theoretical matching boundaries and show the limitations they implicate for real-world amplifier design. Starting with a common schematic prototype, we investigate the question of how to realize its electrical response in a densely routed, massively parallelized layout. To that end, we develop a comprehensive study on the application of space-mapping techniques toward the design of high-power amplifiers (HPAs). We derive three reference design procedures and compare their performance in terms of convergence, speed, and practicality when laying out a densely routed HPA interstage matching network. Subsequently, we demonstrate the usefulness of the study by designing the networks of a compact three-stage eight-way wideband HPA in the Ka-band. The processed monolithic microwave integrated circuit features a 1-dB large-signal bandwidth of more than 11 GHz (a fractional bandwidth of 32.8%) and thus covers most of the Ka-band with an output power exceeding 6 W in 3 dB of gain compression. This demonstrates the highest combination of power and bandwidth to date using a reactively matched topology in the Ka-band.
In this article, we report on compact solid-state power amplifier (SSPA) millimeter-wave monolithic integrated circuits (MMICs) covering the 280-330-GHz frequency range. The technology used is a 35-nm gate-length InGaAs metamorphic highelectron-mobility transistor (mHEMT) technology. Two power amplifier MMICs are reported, based on a compact unit amplifier cell, which is parallelized two times using two different Wilkinson power combiners. The Wilkinson combiners are designed using elevated coplanar waveguide and air-bridge thin-film transmission lines in order to implement low-loss 70-Ω lines in the back-endof-line of this InGaAs mHEMT technology. The five-stage SSPA MMICs achieve a measured small-signal gain around 20 dB over the 280-335-GHz frequency band. State-of-the-art output power performance is reported, achieving at least 13 dBm over the 286-310-GHz frequency band, with a peak output power of 13.7 dBm (23.4 mW) at 300 GHz. The PA MMICs are designed for a reduced chip width while maximizing the total gate width of 512 µm in the output stage, using a compact topology based on cascode and common-source devices, improving the output power per required chip width significantly.
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