In wireless networks with a low duty cycle, the radio is operational for only a small percentage of the time. A sleep timer is used to synchronize the data transmission and reception. The total system power is then limited by the sleep power and the sleep timer frequency stability. Low-frequency crystal oscillators are a common choice for sleep timers due to their excellent long-term stability, frequency stability over temperature, and very low power consumption. However, the external crystal cost and board area are undesired. If an integrated oscillator is used as an alternative, the frequency variation must be minimized so the sleep time can be maximized.Several integrated oscillators with good frequency stability have been proposed in recent publications. In [1], feed-forward correction is used to achieve a stable frequency over temperature, but the voltage sensitivity and die area are large. In [2], self-chopping is used and excellent stability results are achieved at the cost of relatively high power consumption. In [3], offset cancellation is used to allow lower power operation while achieving stable temperature performance. However, long-term stability is limited by flicker noise to 20ppm for intervals over 0.5s. Also, low power systems may have supplies that are allowed to droop while in sleep, so improved frequency stability over supply variation is desired. In this work, an RC oscillator with improved long-term stability and frequency stability over supply voltage is presented.As shown in Fig. 17.8.1, the implemented RC oscillator consists of an RC network, and an inverting gain element from a resistor terminal to a capacitor terminal and another inverting gain element from the common resistor/capacitor terminal back to the resistor terminal. For high gain, the two inverting elements consist of three and five inverters, respectively. A simple regulator, consisting of an NMOS voltage follower and a replica inverter that is flipped and biased by a reference current, produces a local regulated supply for the inverters. This local supply is well below the standard core voltage for the technology. Therefore the inverters have very low average current because they are biased in weak inversion at their switching point.To analyze the frequency variation due to noise and other non-idealities, we define the relative inverter switching point as K SW =V SW /VDD LOCAL or, in other words, the ratio between the input=output inverter switching voltage V SW and the local supply voltage VDD LOCAL . Ignoring inverter delays and output resistance, the voltage at the common RC node will swing from (K SW +1)VDD LOCAL to (K SW −1)VDD LOCAL , as shown in Fig. 17.8.2. It can be shown that the ideal oscillation period equals When K SW =0.5, we get 50% duty cycle, oscillation period t 0 = RC•ln(9) ≈ 2.2RC and the lowest sensitivity to K SW variation.For a low frequency oscillator like this, the inverters driving the resistor and the capacitor will have much lower output resistance than the resistor R, and therefore contribute lit...
The emerging Internet of Things (IoT) market is fueled by reductions in power, cost and size of wireless sensors. Wireless nodes reduce average power by using intermittent data transmission, which is synchronized by a continuously operating sleep timer in each node. In some applications, such as disposable sensors, low cost and small physical size are more important than achieving the lowest possible power consumption. Crystal cost and size is a limitation, particularly because each node requires two crystals. The first crystal, in the MHz range, is used to generate the PLL reference clock. The second crystal, usually 32.768kHz, is used to generate an accurate sleep timer used for synchronizing data transmission. A radio SoC may occupy 4x4mm 2 board area while a standard size for each crystal is 3.2x2.5mm 2 . Therefore, the size of the crystals can be larger than the SoC itself, limiting the applications.The power profile for a wireless node with synchronized data transmission is shown in Fig. 5.9.1. The node spends the majority of time in sleep, T S . To ensure that the wireless link is maintained, a guard time of length T S V S is required, where V S is the maximum frequency variation of the sleep timer due to temperature and voltage shifts. During this guard time, the radio circuits are operational with power P A , waiting for data to be received. Therefore, the energy required that is not directly used for data transmission or reception is limited by the sleep power and the sleep timer frequency stability, and is approximately T S (P S +P A V S ). The term P S +P A V S should be minimized for maximum efficiency. Crystal oscillators have low frequency variation and low power consumption at the cost of increased board area and cost.Recent literature has proposed alternatives to external 32kHz crystals for sleep timers. In [1], an integrated RC oscillator with self-chopping is used and excellent stability results are achieved. However, temperature compensation is required to meet the ±500ppm sleep timer requirement in the Bluetooth Smart standard. In both [2] and [3], a poly resistor with a dedicated temperature coefficient implant is used in the oscillator, which increases the process cost. In [2], frequency variation with supply is also large. Wireless nodes often have supplies that droop while in sleep; so improved frequency stability over supply variation is desired. In [4], a 38.4MHz crystal oscillator is operated in a low power mode (LPM) or high performance mode (HPM) and a 32kHz clock is generated with a divider. This cellular design switches modes without maintaining the time base because a base station is available as the master time reference, unlike for wireless connectivity standards such as Bluetooth Smart or Zigbee. In this work, a dual mode crystal oscillator is presented which maintains the time base when switching between modes, and therefore can be used as a sleep timer as well as a PLL reference clock. The dual mode system block diagram is shown in Fig. 5.9.2. A Pierce oscillator is implement...
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