Integrated Voltage Regulators (IVRs) are attractive substitutes for conventional voltage regulators located on the motherboards, due to outstanding dynamic performances and superior power densities. IVRs operate with switching frequencies in the range of 100 MHz and are assembled in highly compact packages close to the microprocessor load. This paper presents a comprehensive characterization of a PCB-and inductorbased four-phase ANPC-type IVR that uses a Power Management IC (PMIC) implemented in a 14 nm CMOS technology node. The characterization is based on the results of electrical measurements, thermal inspections of the chip surface, and simulations, which enables the separation of the total losses into on-chip and off-chip loss components and the allocation of important loss components inside the chip. The investigated IVR achieves a maximum efficiency of 84.1 % at an output power of Pout = 640 mW and a switching frequency of fs = 50 MHz. The thermal measurements reveal that the maximum efficiency of the PMIC itself is between 88 % and 90 % at fs = 50 MHz and Pout ∈ [500 mW, 600 mW]; at Pout = 890 mW, a chip current density of 24.7 A/mm 2 is achieved. The findings in particular point out that the losses in the chip-internal interconnections, i.e., the conductors of the Power Distribution Network (PDN) and the twelve stacked metal layers below the PDN, have a substantial contribution to the total losses. Furthermore, the combination of Cadence post-layout simulations with impedance networks obtained from an appropriate software tool, e.g., FastHenry, is found to establish a suitable toolbox for estimating losses in IVRs.

Abstract-Integrated Voltage Regulators (IVRs) have become a viable solution for microprocessor's power delivery. The active parts of the most recent IVRs are built in deep-submicron CMOS technologies and use stacked transistors to allow for the use of advanced low voltage devices with superior switching performance compared to the higher voltage long-channel devices. This paper evaluates three different topologies of CMOS half-bridge converters with respect to efficiency, implementation effort, suitability for on-chip integration, and multiphase applications: the conventional half-bridge converter, the half-bridge converter with conventional Active Neutral Point Clamping (ANPC), and a halfbridge converter with a modified circuit to achieve ANPC. Indepth analysis of the transient processes during switching for all three converters, based on Cadence simulations, reveal that both half-bridge converters with ANPC achieve proper balancing of the blocking voltages of the main transistors and are capable to attain similar efficiencies of 93% at an output power of 200 mW, input and output voltages of 1.6 V and 0.8 V, respectively, and a switching frequency of 150 MHz, which is 1% higher than the one attained with the conventional half-bridge converter. Of the two ANPC half-bridge converters, however, the proposed topology allows to completely turn off its entire power stage or parts of it, features less efficiency sensitivity to variations of dead-time, and achieves the peak efficiency at relatively higher dead-time values. These qualities render the proposed topology particularly suitable for multiphase systems and low load operation.

This paper details efficiency optimized operation and design of a bi-directional and isolated five-level Dual Active Bridge (5LDAB) converter for an application that requires ultra-wide voltage and power ranges. The rated power of the considered converter is 7.5 kW, the specified input voltage range is 150 V ≤ V dc1 ≤ 800 V and the output voltage is constant, V dc2 = 700 V. In order to achieve high efficiency levels in a wide operating range, a modulation scheme is proposed to minimize the transformer rms current. Results of transformer rms currents and of efficiencies are presented for the 5LDAB and compared with the results obtained for an efficiency optimized conventional Dual Active Bridge (DAB) converter. Compared with the DAB topology, the 5LDAB converter can achieve an overall reduction of transformer rms currents and of conduction losses in the higher voltage regime of the operating range.Index Terms-DC/DC, Dual active bridge, DAB, Multilevel, Wide voltage range, Efficiency.

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