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As CMOS technology feature sizes decrease, random within-die and inter-die process variations more and more jeopardizeSoCparametricandfunctionalyield.Largely neglectedintheState-Of-the-Art,dynamicenergyconsumption and power dissipation becomes heavily affected. This paper describes a technique to systematically bring statistically correlated timing/energy variations all the way up from the device to the SoC level. We propose a flow for Variability Aware Modeling (VAM) and apply it to a case study using a industrial test vehicle.978-1-4244-2953-0/09/$25.00

If adjacent wires are brought into a simple specific order of their switching activities, the effect of power optimal wire spacing can be increased. In this paper we will present this order along with a prove of this observation. For this purpose, it is shown how to derive the new power optimal wire positions by solving a geometric program. Due to their simplicity in implementation, both principles reported substantially differ from previous approaches. We also quantify the power optimization potential for wires based on a representative circuit model, with promising results.

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An increasing fraction of dynamic power consumption can be attributed to switched interconnect capacitances. Nonuniform wire spacing depending on activity had shown promising power reductions for on-chip buses. In this paper, a new and fast routing optimization methodology based on non-uniform spacing is proposed for entire circuits. No area investment is required, since whitespace remaining after detailed routing is exploited. The proposed methodology has been implemented and tapped into an industry-proven design flow. Wire power reductions of up to 9.55% for modern multiprocessor benchmarks with tight area constraints are demonstrated, twice as much as approaches that do not take switching activities into account. Timing is not adversely affected, and the yield limit is slightly improved.Index Terms-Interconnect topology optimization, low-power, switching activity driven, wire spacing.