Variability aware modeling of SoCs: From device variations to manufactured system yield

Miranda, M.; Dierickx, B.; Zuber, Paul; Dobrovoln, P.; Kutscherauer, F.; Roussel, Ph.; Poliakov, Pavel

doi:10.1109/isqed.2009.4810353

Cited by 15 publications

(14 citation statements)

References 19 publications

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“…From costly Monte Carlo analysis to probabilistic methods, these techniques are usually focused on improving timing yield at circuit level, where variations can cause up to 30% of mismatch in chip frequency [Agarwal et al 2003;Forzan and Pandini 2009]. Other techniques based also on statistical characterization can be found in [Miranda et al 2009]. Most of the work done in statistical analysis assumes that key parameters affected by variability, such as the threshold voltage or the effective channel length, follow a multivariate normal distribution [Herbert and Marculescu 2009].…”

Section: Related Workmentioning

confidence: 99%

System-level memory management based on statistical variability compensation for frame-based applications

Sanz

Gómez

Tenllado

et al. 2013

ACM Trans. Embed. Comput. Syst.

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Process variability and dynamic domains increase the uncertainty of embedded systems and force designers to apply pessimistic designs, which become unnecessarily conservative and have a tremendous impact on both performance and energy consumption. In this context, developing uncertainty-aware design methodologies that take both variation at platform and at application level into account becomes a must. These methodologies should mitigate the effects derived from uncertainty, avoiding worst-case assumptions. In this article we propose a comprehensive methodology to tackle two forms of uncertainty: (1) process variation on the memory system, (2) application dynamism. A statistical model has been developed to deal with variability derived from fabrication process, whereas system scenarios are selected to cope with dynamic domains. Both sources of uncertainty are firstly tackled in combination at design time, to be refined later, at setup. As a result, at run time the platform can be successfully adapted to the current application behaviour as well as the current variations. Our simulations show that this methodology provides significant energy savings while still meeting strict timing constraints.

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Section: Related Workmentioning

confidence: 99%

System-level memory management based on statistical variability compensation for frame-based applications

Sanz

Gómez

Tenllado

et al. 2013

ACM Trans. Embed. Comput. Syst.

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“…For this variation, we assumed a standard deviation of 3.3% (3σ = 10%) for all three resources. These numbers are selected as they agree with the data on process variation in current technology nodes [5]. To obtain the set of possible operating points, we discretized the FMAX probability distribution function (PDF) of each resource into 5 discrete points.…”

Section: A Setupmentioning

confidence: 99%

“…This phenomenon, known as process variation [1], [2], significantly impacts the maximum supported frequency of individual cores in a MPSoC [3], [4]. It is shown in [5] that the variation in the longest path delay (the inverse of FMAX) of a Very Long Instruction Word (VLIW) processor, manufactured at 32nm technology, is up to 40%. Moreover, the impact of within-die variation on the system parameters is increasing as the technology scales, making it a limiting factor in efficient MPSoC design [3].…”

Section: Introductionmentioning

confidence: 99%

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Mirzoyan

Åkesson

Goossens

2012

Thirteenth International Symposium on Quality Electronic Design (ISQED)

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A bs tr act -As t echnology s cales , t he impact of proces s variat ion on the maximum supported frequency (FMAX) of individual cores in a MPSoC becomes more pronounced. Task allocation without variation-aware performance analysis can result in a significant loss in yield, defined as the number of manufactured chips satisfying the application timing requirement. We propose variation-aware task allocation for real-time streaming applications modeled as task graphs. Our solutions are primarily based on the throughput requirement, which is the most important timing requirement in many real-time streaming applications. The three main contributions of this paper are: 1) Using data flow graphs that are well-suited for modeling and analysis of real-time streaming applications, we explicitly model task execution both in terms of clock cycles (which is independent of variation) and seconds (which does depend on the variation of the resource), which we connect by an explicit binding. 2) We present two approaches for optimizing the yield. The approaches give different results at different costs. 3) We present exhaustive and heuristic algorithms that implement the optimization approaches. Our variation-aware mapping algorithms are tested on models of real applications, and are compared to the mapping methods that are unaware of hardware variation. Our results demonstrate yield improvements of up to 50% with an average of 31%, showing the effectiveness of our approaches.

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“…A generic analytical approach to predict the statistics of a system from the given Probability Density Function (PDF) of its sub-system components appeared in [9], and particularly for memories in [10]. However, both methods fail to accurately capture all the interactions between the different memory islands.…”

Section: Related Workmentioning

confidence: 99%

Statistical SRAM analysis for yield enhancement

Zuber¹,

Miranda²,

Dobrovolný³

et al. 2010

2010 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE 2010)

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This paper presents an automated technique to perform SRAM wide statistical analysis in presence of process variability. The technique is implemented in a prototype tool and is demonstrated on several 45 and 32nm industry-grade SRAM vehicles. Selected case studies show how this approach successfully captures non-trivial statistical interactions between the cells and the periphery, which remain uncovered when only using statistical electrical simulations of the critical path or applying a digital corner approach. The presented tool provides the designer with valuable information on what performance metrics to expect, if manufactured. Since this feedback takes place in the design phase, a significant reduction in development time and cost can be achieved.

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Variability aware modeling of SoCs: From device variations to manufactured system yield

Cited by 15 publications

References 19 publications

System-level memory management based on statistical variability compensation for frame-based applications

System-level memory management based on statistical variability compensation for frame-based applications

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield

Statistical SRAM analysis for yield enhancement

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