New concept of interposer in FPGA system will be introduced. The interposer includes a lot of TSVs for the high speed signals. Technology requirements and manufacturing process to support multi-gigabit or tens-of-gigabit per second SerDes application will be presented. The interposer needs to be accurately modeled over the high frequency by considering all those requirements before design optimization. An interposer test vehicle was fabricated for measurement and verification. The measurement technique using vector network analyzer including de-embedding process will be introduced. At the same time, TSV high frequency modeling methodology will be disclosed. Both broadband s-parameter model and RLC lumped model based on physical structures were generated. The interposer could be a passive component or an active component with circuit. The passive interposer has an advantage in a certain area and the active interposer also has its own. The depletion area in silicon substrate will be considered as well to increase the level of accuracy. The routing metal loss in under bump metallurgy (UBM) layer should be analyzed also. Finally, full channel analysis has been done. It includes optimized interposer model on top of package substrate and printed circuit board. Each proposed interposer structure enables high performance signaling and great visibility in both passive and active interposer. Introduction: Overview of Stacked Silicon Interposer TechnologyFPGA-based solutions can provide the system-level functionality currently delivered by ASICs and ASSPs. The requirements for a viable solution include increased capacity, lower power, and higher bandwidth. The most aggressive adopters of FPGA technology are eager to employ the highest capacity and bandwidth device of new FPGA generation. However, the challenges of building large FPGAs early in the production life cycle can limit the ability to supply the volumes of devices because at the early stages of a new process node, when defect densities are high, die yield declines dramatically as die size increases. To address these issues, Xilinx has introduced stacked silicon interconnect technology to provide a modular and highly manufacturable method to build high gate count and resource-rich FPGAs [1]. The enabling technologies in stacked silicon interconnect technology are silicon interposer with high-density interconnects, through silicon vias (TSVs), and fine-pitch micro-bumps. These technologies make possible manufacture FPGAs that offer bandwidth and capacity exceeding that of the largest possible monolithic FPGA die with the manufacturing and time-to-market advantages of smaller die.
Multi-gigabit serial channel design has become more and more important since channel margins are becoming tighter as operating frequencies increase. Most engineers working on these channels have been plagued by several different types of signal integrity problems including impedance discontinuities, reflections, attenuation, undershoot and overshoot, and crosstalk. In reality, many signal integrity problems are caused by impedance discontinuities. These discontinuities can be caused by physical discontinuities, system parasitics, or design mistakes. We need to understand these discontinuity issues to improve full channel from package to PCB board. When most designers simulate a channel, they concatenate separate package and PCB models. Using these concatenated models they simulate the data path in a channel simulation test bench. This piecewise or concatenated channel model is incomplete because it does not carefully consider the interface between the BGA package and the PCB.The hidden factor which makes the concatenated channel model differ from real channel measurement will be disclosed in this paper. A more detailed solder ball analysis has also been done during this process. We learn from the above results that if the package is soldered down to the PCB and measured together, additional loss occurs due to the package to board transition. The combined channel is more capacitive than the concatenated channel in the package to board transition region. The excess capacitance due to BGA solder ball transition is due to the physics of the interface and can not be easily eliminated. It is shown that system performance degradation is very sensitive to the impedance discontinuity introduced at the BGA/PCB interface. This paper will introduce a spiral via structure which is shown to be a more effective way to compensate the transition discontinuity seen at the BGA/PCB interface. This paper also shows how the spiral via structure was implemented and optimized in the BGA package. The overall channel performance improvement by using spiral via structures in BGA package is proven by the simulation and measurement.
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