Interconnect and package design of a heterogeneous stacked-silicon FPGA

Wu, Ephrem; Abugharbieh, Khaldoon; Banijamali, Bahareh; Ramalingam, Suresh; Wu, Paul; Wyland, Chris

doi:10.1109/cicc.2013.6658402

Cited by 8 publications

(3 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…7. The Virtex-7 family FPGA used in this experiment is one the largest FPGA available at the time of the experiment and internally has 4 different silicon integrated circuits (ICs) called super logic regions (SLRs) connected by stacked silicon interconnect (SSI) technology [15]. A special challenge can arise from the multi-IC FPGA architecture as opposed to ASIC counterparts due to the relatively limited number of available interconnects between neighboring SLRs and the long delay when the connection is made across multiple SLRs.…”

Section: Methodsmentioning

confidence: 99%

Field Demonstration of 100-Gb/s Real-Time Coherent Optical OFDM Detection

Kaneda¹,

Pfau²,

Zhang

et al. 2015

J. Lightwave Technol.

View full text Add to dashboard Cite

We report the field demonstration of 100-Gb/s realtime coherent optical orthogonal frequency-division multiplexing (CO-OFDM) detection using polarization division multiplexed QPSK modulation per subcarrier. The paper includes one of the lowest BER ever reported for a CO-OFDM back-back transmission experiment at 5 × 10 −9 and the successful 495.2-km transmission over mixed types of field installed fiber. The field trial is conducted in a dispersion managed WDM system with neighboring 10-Gb/s Ethernet channels.Index Terms-Orthogonal frequency division multiplexing (OFDM), CO-OFDM, quadrature phase-shift keying (QPSK), coherent detection, real-time signal processing, optical subsystem.

show abstract

Section: Methodsmentioning

confidence: 99%

Field Demonstration of 100-Gb/s Real-Time Coherent Optical OFDM Detection

Kaneda¹,

Pfau²,

Zhang

et al. 2015

J. Lightwave Technol.

View full text Add to dashboard Cite

show abstract

“…In contrast to that, publications describing interconnect lines on an interposer are relatively rare. Reference [2] gives some insights to a sliced FPGA design on interposer. It turns out that the most chip-to-chip interconnections are smaller than 5 mm and the shielded interconnections are running with 200 MHz.…”

Section: State Of the Artmentioning

confidence: 99%

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Dittrich

Steinhardt

Heinig

et al. 2015

2015 IEEE 65th Electronic Components and Technology Conference (ECTC)

View full text Add to dashboard Cite

Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip in a side-by-side interposer approach. We investigate the performance of interconnections on a typical silicon interposer with polymer applied to the redistribution layer on both sides using electromagnetic simulations. The simulations are valued by measurements. Our measurements show that microstrip lines with <0.3 dB/mm insertion loss at 30 GHz can be achieved with a typical polymer based interposer process. In contrast to other work we extend the microstrip line model with pads on both ends to form a complete interconnection. Our investigations show that an insertion loss of <0.55 dB/mm can be achieved assuming dense inter-connections. We investigate the impact of technological variations during the manufacturing process of a silicon interposer. This is important to ensure electrical functionality (signal and power integrity) of the system in mass production. The results on technology variations during the manufacturing process of an interposer show that variations of 20 % in trace width and trace height are changing the characteristic impedance of the line, but do not significantly affect the signal integrity of sufficiently long lines. In contrast, variations of 20 % in polymer height and polymer permittivity in the redistribution layer have more influence on signal integrity of sufficiently long interposer interconnections

show abstract

“…But the interposer interconnections are expected to be much shorter than the average PCB interconnections because the bare dies are directly next to each other. In fact, the investigations from a practical implementation in [1] show that just a small fraction of the chip-to-chip interconnections does exceed 5 mm. Thus, the DC resistance, capacitance and inductance per length of the interposer interconnection will be a decade smaller compared to a 50 mm PCB transmission line.…”

Section: A Experimental Setup and Extractionmentioning

confidence: 99%

Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer

Dittrich

Heinig

2015

2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)

View full text Add to dashboard Cite

Silicon interposers enable the heterogeneous integration of high performance systems. This paper focuses on interconnections from one chip to a neighboring chip via an interposer. We use a typical silicon interposer with polymer applied to the redistribution layer on both sides and line/space of 10 µm. We point out important advantages and differences of the chip-to-chip interconnection in comparison to usual integration using a separate package for each chip and a printed circuit board. The electrical behavior of the interconnections is simulated. The results demonstrate a 2 Gbps communication on a 9 mm long interposer interconnection. The average power consumption of a state transition of the chip-to-chip interconnection is simulated and compared to the power consumption of a typical PCB transmission line. The results show that the interposer interconnection consumes significantly more power per length than a typical PCB trace because of his increased resistance. Because of that we recommend to not decrease the line/space beyond 10 µm for chip-to-chip interconnections

show abstract

Interconnect and package design of a heterogeneous stacked-silicon FPGA

Cited by 8 publications

References 3 publications

Field Demonstration of 100-Gb/s Real-Time Coherent Optical OFDM Detection

Field Demonstration of 100-Gb/s Real-Time Coherent Optical OFDM Detection

Characteristics and process stability of complete electrical interconnection structures for a low cost interposer technology

Investigation of chip-to-chip interconnection structures for high data rates on a low cost silicon interposer

Contact Info

Product

Resources

About