Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology

Kim, Nam Hoon; Wu, Daniel; Carrel, Jack; Kim, Joong-Ho; Wu, Paul

doi:10.1109/ectc.2012.6249080

Cited by 15 publications

(3 citation statements)

References 3 publications

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“…[3] It's more like a saucer that different chips or passive devices can be placed on it and be connected to each other by the copper lines in its redistribution layers and TSVs. Consequently, multi-functions and high density integration can be easily achieved.…”

Section: The Structure Of Interposermentioning

confidence: 99%

Full channel simulation for high speed 2.5D package with silicon interposer

Wang

Liu²

2013

2013 14th International Conference on Electronic Packaging Technology

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In this paper, a full channel simulation model of interposer and organic substrate is established. The TSV (through silicon via) interposer provides highbandwidth, low-latency interconnection to accomplish higher performance and reach smaller size of the semiconductor devices. For 2.5D packaging, it's extremely necessary and pressing to estimate the electrical property and optimize the structure for TSV interposer. The model of ground-signal-signal-ground (GSSG) coplanar lines of differential pair in redistribution layer (RDL) on the interposer with TSVs is simulated by Ansoft's HFSS. In addition, another strip line model of this differential pair in organic substrate is simulated. Then a co-simulation method of the full channel is proposed utilizing Agilent's ADS. By using the simulation approach, the signal quality of this channel is presented and some signal integrity (SI) issues are discussed by analyzing the S-parameter and eye diagram.

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Section: The Structure Of Interposermentioning

confidence: 99%

Full channel simulation for high speed 2.5D package with silicon interposer

Wang

Liu²

2013

2013 14th International Conference on Electronic Packaging Technology

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“…Crosstalk is noise from capacitive and inductive couplings in adjacent channels [45][46][47]. Typically, the amount of far-and near-end crosstalk is proportional to the data rate and the number of aggressors.…”

Section: A Signal Noise: Crosstalkmentioning

confidence: 99%

Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review

Park,

Kim

2024

IEEE Access

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An eye diagram, a critical metric in signal integrity analysis for high-speed interconnects such as packages, interposer, and printed circuit boards (PCBs), is generated by superposition of the received waveform. Obtaining an eye diagram is time-consuming, thus signal integrity analysis is inefficient. This article reviews that have been proposed to overcome this limitation. The statistical eye diagram provides a probability distribution depending on a sampling time and voltage, therefore it can be expanded to other metrics, such as the bit-error rate and shmoo plot. This article introduces previous research on statistical eye diagrams applied to complementary metal-oxide-semiconductors (CMOSs), noise, and high-speed systems. The methods applied to CMOSs include asymmetry between the P/NMOS transistors and the nonlinearity of the CMOS. The methods applied to noise include signal and power noise. The methods applied to high-speed systems include equalizers, signaling, encoding, linear feedback shift register, and error correction code.INDEX TERMS Complementary metal-oxide-semiconductor (CMOS), crosstalk, double edge response (DER), error correction code (ECC), encoding, equalizer, eye diagram, multiple edge response (MER), pulse amplitude modulation (PAM), package, single bit response (SBR), signal integrity (SI), statistical eye diagram.

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“…Because the number of I/O in the silicon interposer cannot be infinitely increased due to routability issues, a wider bandwidth per channel is required. For example, the required data rate of a single chip-tochip channel of the Virtex-7 HT field programmable gate array (FPGA) from Xilinx, which is based on the silicon interposer, is near 30 Gb/s [3]. However, as the data rate of the silicon-based on-interposer channel increases, the considerable frequency-dependent loss from the silicon substrate crucially limits the high-speed data transmission.…”

Section: Introductionmentioning

confidence: 99%

A Wideband On-Interposer Passive Equalizer Design for Chip-to-Chip 30-Gb/s Serial Data Transmission

Kim

Cho

Kim

et al. 2015

IEEE Trans. Compon., Packag. Manufact. Technol.

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In this paper, a novel on-interposer passive equalizer is proposed for chip-to-chip high-speed data transmission on the silicon-based on-interposer channel. The proposed equalizer uses the parasitic resistance and inductance of the on-interposer shunt metal lines to produce the high-pass filter. This filter enables the proposed equalizer to exhibit wideband channel equalization and low power-consumption. Based on the equivalent-circuit model of the proposed on-interposer passive equalizer, the physical dimensions of the equalizer are optimized for 30-Gb/s serial data transmission. The performance of the proposed equalizer with the optimized dimensions was successfully demonstrated by both frequency-and time-domain measurements at data rates of up to 30 Gb/s. In addition, a compact on-interposer passive equalizer was designed for the wide I/O interposer using the same mechanism. The improved quality of serial data transmission in the equalized wide I/O on-interposer channel was successfully verified by simulations at data rates of up to 10 Gb/s. Index Terms-Intersymbol interference (ISI), on-interposer passive equalizer, silicon-interposer, wide I/O, wideband.

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Channel design methodology for 28Gb/s SerDes FPGA applications with stacked silicon interconnect technology

Cited by 15 publications

References 3 publications

Full channel simulation for high speed 2.5D package with silicon interposer

Full channel simulation for high speed 2.5D package with silicon interposer

Statistical Eye Diagrams for High-Speed Interconnects of Packages: A Review

A Wideband On-Interposer Passive Equalizer Design for Chip-to-Chip 30-Gb/s Serial Data Transmission

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