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Nanophotonic is a promising solution for on-chip interconnection due to its intrinsic low-latency and low-power features. Future tiled chip multiprocessors (CMPs) for rich client devices can receive energy benefits from this technology but we show that great care has to be put in the integration of the various involved facets to avoid queuing and serialization issues and obtain the rated potential advantages. We evaluate different management strategies for accessing a simple, shared photonic path (ring), working in conjunctions with a standard electronic mesh or alone, in a tiled CMP. Our results highlight that a careful selection of the most latency-critical messages to be routed in photonics and the use of a conflict-free access scheme is crucial for obtaining performance/power advantages when the available bandwidth is limited. We identify the design point where all the traffic can be routed on the photonic path and thus the electronic network can be suppressed. At this point, the ring achieves 20--25% speedup and 84% energy consumption improvement over the electronic baseline. Then we investigate the same trade-offs when the number of rings is increased up to eight, allowing to raise performance benefits up to 40% or reaching up to 80% energy reduction. We finally explore the effects of deploying a given optical parallelism split between a higher number of waveguides for further improving energy savings.

Nanophotonic interconnection is a promising solution for inter-core communication in future chip multiprocessors (CMPs). Main benefits derive from its intrinsic low-latency and high-bandwidth, especially when employing wavelength division multiplexing (WDM), as well as reduced power requirements when compared to electronic NoCs. Existing works on optical NoCs (ONoC) mainly concentrate on relatively complex proposals needed to host the whole CMP traffic. In some proposals complexity is increased also from the need of an electronic network for preliminary pathsetup in the optical one. This paper proposes to enhance a conventional NoC with only a simple photonic structure, a ring, and aims at investigating its suitability to support the low-latency transmission of small latency-critical coherency control messages as to improve performance of multithreaded applications. In particular, our proposed scheme supports fast multicast transmission of invalidation messages. We have simulated Parsec benchmarks on an 8 core full-system CMP. Results show that a careful selection of coherency control messages to be forwarded to the photonic ring allows improving execution time up to 19%, with an average of 6% across all considered benchmarks. We discuss how different selections of messages, i.e. related to read and/or write operations, affect results and single out the most profitable set. Moreover, we show that the sharing behavior of benchmarks has a central role in the final performance.

ERIS is an instrument that will both extend and enhance the fundamental diffraction limited imaging and spectroscopy capability for the VLT. It will replace two instruments that are now being maintained beyond their operational lifetimes, combine their functionality on a single focus, provide a new wavefront sensing module that makes use of the facility Adaptive Optics System, and considerably improve their performance. The instrument will be competitive with respect to JWST in several regimes, and has outstanding potential for studies of the Galactic Center, exoplanets, and high redshift galaxies. ERIS had its final design review in 2017, and is expected to be on sky in 2020. This contribution describes the instrument concept, outlines its expected performance, and highlights where it will most excel.