A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs

Abstract

Nanophotonic interconnection is a promising solution for inter-core communication in future chip multiprocessors (CMPs). Main benefits derive from its intrinsic low-latency and high-bandwidth, especially when employing wavelength division multiplexing (WDM), as well as reduced power requirements when compared to electronic NoCs. Existing works on optical NoCs (ONoC) mainly concentrate on relatively complex proposals needed to host the whole CMP traffic. In some proposals complexity is increased also from the need of an electronic network for preliminary pathsetup in the optical one. This paper proposes to enhance a conventional NoC with only a simple photonic structure, a ring, and aims at investigating its suitability to support the low-latency transmission of small latency-critical coherency control messages as to improve performance of multithreaded applications. In particular, our proposed scheme supports fast multicast transmission of invalidation messages. We have simulated Parsec benchmarks on an 8 core full-system CMP. Results show that a careful selection of coherency control messages to be forwarded to the photonic ring allows improving execution time up to 19%, with an average of 6% across all considered benchmarks. We discuss how different selections of messages, i.e. related to read and/or write operations, affect results and single out the most profitable set. Moreover, we show that the sharing behavior of benchmarks has a central role in the final performance.

From hybrid electro-photonic to all-optical on-chip interconnections for future CMPs

“…For such short messages the average latency introduced by the step-by-step path-setup procedure is longer than the transmission time. The effect is even amplified for those coherence messages that are on the critical path for the cores [13]. For further details [15].…”

“…Results are not shown here for space reason. The main contribution of this work [13], is the careful selection of the most latency-critical cache coherence messages to be forwarded on a narrow path.…”

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects

“…From our simulation environment, described more in detail in Section IV-A, we counted that more than 80% of the total traffic is control messages in the considered PARSEC [10] benchmarks. In general, directory-based coherency systems intrinsically need to rely on multiple control message transmissions for each protocol transaction [2], [11], [12]. These messages, being typically far smaller than data ones (e.g., 8 bytes compared to 32-64 bytes) benefit more from decreasing end-to-end transmission latency than from increasing bandwidth (transmission parallelism or frequency).…”

“…On-chip nanophotonic technology (ONoC) is now considered a promising solution for fulfilling the low-latency and high-bandwidth communication requirements of future Chip Multi-Processor systems (CMPs) [1], [2]. These systems are very demanding from the memory bandwidth point of view because of the aggregate requirements of the constantly increasing number of cores per chip [3], [4].…”

Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors

“…To help bridge this gap, this paper proposes Olympic, a flexible clustered all-optical NoC architecture suitable for managing cache-coherent CMP traffic, for which the latency of message sequences is very important [2], and to specifically address low-energy operation. Olympic employs a lowcomplexity hierarchical topology made up of a replicated and cascaded simple building blocks (i.e., photonic rings) without using optical switches.…”