FPGAs which are configured by static RAM can be rapidly changed from one logic configuration to another. This raises the possibility of configuring the logic to implement a function for a specijic set of values, i.e. folding the inputs into the logic design. The paper discusses data folding with respect to Algotronljr FPGAs, presenting a text searching circuit as an example. This folded circuit saves at least hay the logic over a conventional circuit, and very much more if data folding is taken as far as possible. It also presents performance figures for the folded circuit, and discusses other applications, and suggests features which are desirable if data folding is to be practicable, most of which are possessed by the Algotronix CAL array.
The algorithmic, electronic, and optical aspects of the implementation of a perfect-shuffle interconnected bitonic sorter are analyzed. The performance metrics such as the bit output data rate and the power consumption of the system are quantified. The sorting module is designed to demonstrate the parallel nonlocal interconnection of smart-pixel arrays and the use of optical-image control masks in a functioning information processor.
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