Adaptive-logic trees for use in multilevel-circuit design

Green, D.H.; Foulk, P.W.

doi:10.1049/el:19690059

Cited by 4 publications

(2 citation statements)

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“…Arithmetic functions like counters, adders, multipliers, signal processing functions and error correcting logic that belong to the class of (nearly) linear functions 16] cannot be efficiently minimized for circuit speed and area using BDDs only. To address these deficiencies, the concepts of: Adaptive logic trees [14] and Functional Decision Diagrams (FDDs) [33,18] have been developed and applied to FPGA mapping. The adaptive logic trees were introduced for multi-level representation of switching functions based on Reed-Muller [10] canonical expansion.…”

Section: Introductionmentioning

confidence: 99%

Multi‐Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

et al. 1995

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This paper introduces several new families of decision diagrams for multi-output Boolean functions. The introduced families include several diagrams known from literature (BDDs, FDDs) as subsets. Due to this property, these diagrams can provide a more compact representation of functions than either of the two decision diagrams. Kronecker Decision Diagrams (KDDs) with negated edges are based on three orthogonal expansions (Shannon, Positive Davio, Negative Davio) and are created here for incompletely specified Boolean functions as well. An improved efficient algorithm for the construction of KDD is presented and applied in a mapping program to ATMEL 6000 fine-grain FPGAs. Four other new families of functional decision diagrams are also presented: Pseudo KDDs, Free KDDs, Boolean Ternary DDs, and Boolean Kronecker Ternary DDs. The last two families introduce nodes with three edges and require AND, OR and EXOR gates for circuit realization. There are two variants of each of the last two families: canonical and non-canonical. While the canonical diagrams can be used as efficient general-purpose Boolean function representations, the non-canonical variants are also applicable to incompletely specified functions and create don't cares in the process of the creation of the diagram.. They lead to even more compact circuits in logic synthesis and technology mapping.

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Section: Introductionmentioning

confidence: 99%

Multi‐Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

et al. 1995

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“…Based on the Shannon Expansion of the two-level fixed-polarity Reed-Muller Expansion, there exists a recursively defined multilevel representation [ 16]:…”

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confidence: 99%

Investigation of Solution Space of Trees and DAGs for Realization of Combinational Logic in AT 6000 series FPGAs

Ho¹

2000

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Various tree and Directed Acyclic Graph structures have been used for representation and manipulation of switching functions. Among these structures the Binary Decision DiagramJilave been the most widely used in logic synthesis. A BDD is a binary tree graph that represents the recursive execution of Shannon's expansion. A FDD is a directed function graph that represents the recursive execution of Reed Muller expansion. A family of decision diagrams for representation of Boolean function is introduced in this thesis. This family of Kronecker Functional Decision Diagrams (KFDD) includes the Binary Decision Diagrams (BDD) and Functional Decision Diagrams (FDD) as subsets. Due to this property, KFDDs can provide a more compact representation of the functions than either of the two above-mentioned decision diagrams. The new notion of permuted KFDD is introduced to generate a compact circuit in FPGAs to represent a switching function. A permuted tree search is a free search method which is not limited by the order of variable and the expansion tree as in the cases of KFDD, BDD and FDD. A family of decision diagrams and the theory developed for them are presented in this thesis. The family of permuted Kronecker Functional Decision Diagrams includes BODs and FDDs as subsets is incorporated into program RESPER. Due to this property, permuted KFDD can provide a more compact circuit realization in the multilevel circuit. The circuit obtained can be realized directly with FPGAs like AT 6000 series from Atmel. This algorithm is implemented on several MCNC benchmarks, the results compared with previous programs, TECHMAP and REMIT, are very encouraging.The main achievement of this thesis is the creation of the algorithm which applies a permuted tree search method combined with Davia Expansion and generates Directed Acyclic Graph which is next mapped to a compact circuit realization. 2

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Synthesis for Reed-Muller directed acyclic graph network

Nan²,

Perkowski

1993

IEE Proceedings E (Computers and Digital Techniques)

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Adaptive-logic trees for use in multilevel-circuit design

Cited by 4 publications

References 0 publications

Multi‐Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

Multi‐Level Logic Synthesis Based on KroneckerDecision Diagrams and Boolean Ternary DecisionDiagrams for Incompletely Specified Functions

Investigation of Solution Space of Trees and DAGs for Realization of Combinational Logic in AT 6000 series FPGAs

Synthesis for Reed-Muller directed acyclic graph network

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