Special feature. User configurable logic

Foulk, P.W.

doi:10.1049/cce:19920055

Cited by 3 publications

(3 citation statements)

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“…Due to advances in VLSI technology, it is now possible to build them inexpensively using either custom designs or commercially available field programmable gate arrays such as those from Xilinx, A1-tera, Actel, CAL, Plessey and others [6]. In order to maximize the number of processing elements per VLSI chip and yet get a feasible design, it is necessary to limit the size of each processor, the amount of on-chip storage, as well as the interconnect [7].…”

Section: Introductionmentioning

confidence: 99%

“…It has been shown that long interconnects dominate the delay and limit the efficacy of modern VLSI circuits [8]. Although FPGA's [6] have a programmable interconnect which allows any two logic blocks to be connected, longer routing paths lead to signal propagation delays and degrade the performance.…”

Section: Introductionmentioning

confidence: 99%

“…Specifying the configuration requires a large number of bits. For example, in the ERA (Electrically Reconfigurable Array) from Plessey, eight out of ten instruction bits control the interconnection inputs [6]. By imposing our architectural model, the problem of block placement is trivial and the number of bits required to specify the configuration is considerably less.…”

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confidence: 99%

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Digit pipelined arithmetic on fine-grain array processors

Nagendra

Owens

Irwin

1995

Journal of VLSI Signal Processing

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Abstract. In this paper, we present a novel scheme for performing fixed-point arithmetic efficiently on fine-grain, massively parallel, programmable architectures including both custom and FPGA-based systems. We achieve an O(n) speedup, where n is the operand precision, over the bit-serial methods of existing fine-grain systems such as the DAP, the MPP and the CM2, within the constraints of regular, near neighbor communication and only a small amount of on-chip memory. This is possible by means of digit pipelined algorithms which avoid broadcast and which operate in a fully systolic manner by pipelining at the digit level. A base 4, signed-digit, fully redundant number system and on-line techniques are used to limit carry propagation and minimize communication costs.Although our algorithms are digit-serial, we are able to match the performance of the bit-parallel methods, while retaining low communication complexity. Reconfigurable hardware systems built using field programmable gate arrays (FPGA's) can share in the speed benefits of these algorithms. By using the organization of logic blocks suggested in this paper, problems of placement and routing that exist in such systems can be avoided. Since the algorithms are amenable to pipelining, very high throughput can be obtained.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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