An electronically-programmable d o g circuit (EPAC), hased on switched-capacitor (SC) technique, is an analog counterpart of digital WGAs [l, 41. The full speed potential of analog circuits, however, can be utilized only by continuous-time (CT) fieldprogrammable analog arrays (FPAAs), proposed by References 5 and 8.There me two challenges in the development of analog CT fieldprogrammable devices, The first is providing an mhitectrve (interconnection scheme), complex enough to be called programmable, and yet contributinglittleirence, crosstalk and noise critical problems in analog design. Local sigrd inten;onnedions are recommended in References 9 and 10, where several e m p l e s demonstrate how constraining the interconnedion scheme can be arranged without compromising flexibility of the architecture.The second challenge is designing a flexible, universal unit of an FPAA, a programmable cell. Explicit use of electronic switches in the signal path is discouraged, because switch partwitiw, such ga finite on resistance and stray capacitances, lead to frequency performance degradation, An example of an FPAA structure with local intemnnections is shown in Figure 1, a simplified variant of one proposed in Fkferences 9 andlo. Each cell derives a weighted sum of selected signals from four nearest neighbors, and optionally perf om^ integration (ideal or lossy) to produce its own output signal ( Figure lb).An eightharder elliptic band-pass ladder filter (a current-mode equivalent of one in References 9,ll and 12) is mapped into the FPAA, Dashed lines show unused elements and co~ections. All cells in the structure are identical, but, in the filter they realize three different functions; ideal integration, lossy integration, a d amplification, with parameters vaFying from cell to cell.A straightforward implementation of amplifieatiodmtegration in OTA-C (operational transconductance amplifier and capacitor) technique leads to a capacitor connected to the OTA output via electronic switches, degrading the frequency response 111, 121.The design presented does not use any switches in the signal path.A test circuit, containing the amplifier/integrator core of a cell has been fabricated in a transistor-array process* (Figures 2,3a, 3b). To avoid clutter, auxiliary bias and common-mode feedback circuitry is omitted from the figures. The input buffer 111, Figure 3a, and comprising transistors Q,-Q,, in Figure 2 is based on a current amplifier proposed by Gilbert [2,3]. WhenIEll, QB are off,no signal is passed to the cell (an inactive connection in figure la). m e n one of the sources is on, the signal is transmittedwith optional gain (depepdent on the bias) of up to about 10 [2,31. The buffer also eliminates common-mode signals, and separates high-impedance g, input h m other cells. In the integrating mode sources Icls and I,,, are off (Figure 3a). Outputs of the buffer are connected to the simplified gm cell (Darlington pairs %-a, %-a), and to the capacitors C. A twostage current amplifier 4 (%,-%, Qm-G) follows G. The arrangement ...