A B S T R A C TT o provide flexibility and efficiency in logic and timing verification of M O S V L S I circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. The modeling levels are MOS transistor level, logic gate level and functional level. The simulation levels are t i m i n g , multiple delay and unit delay. The simulator is being used on production LSI chips and its performance is discussed.
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