A B S T R A C T T h i s paper describes a multiple delay simulator for M O S LSI circuits. The basic primitives for this simulator are M O S transistor structures where the transistors are evaluated logically. Integer rise and fall delays are a s s oc i a t e d with each transition and these delays are computed automatically based on device characteristics and circuit capacitances. The simulator has been extensively used for the design verification of production LSI chips.
Bridge is a behavioral synthesis system being developed at AT&T Bell Laboratories. In this system, a variable in a behavioral description can be either a storage element or a signal. The impact of treating a variable as a signal on lifetime analysis is discussed. The feature of supporting both signals and registers for program variables facilitates systematic exploitation of tradeoffs between cost and performance. Intelligent bindings of the variables in a behavioral description to registers and signals not only reduce the implementation cost but also improve the circuit performance. Experimental data for the descriptions of three telecommunication circuits are presented.
A B S T R A C TT o provide flexibility and efficiency in logic and timing verification of M O S V L S I circuits, it is desirable that various portions of a circuit can be described and simulated at appropriate levels of detail. Such a capability is provided by the Mixed-Mode Simulator described here. This simulator allows different elements of a circuit to be modeled and simulated at different levels of detail. The modeling levels are MOS transistor level, logic gate level and functional level. The simulation levels are t i m i n g , multiple delay and unit delay. The simulator is being used on production LSI chips and its performance is discussed.
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