Bellcore has built the SONET Toolkit decision support software to design robust fiber-optic networks that protect services against the consequences of a cable cut (link) or an equipment failure (node). The Synchronous Optical NETwork (SONET) makes these survivable designs cost-effective when planned carefully. The SONET Toolkit reads in data about the network, its embedded capacity, the available equipment, the customer demands, and the protection requirements for the services. It can also incorporate planning constraints. It produces an economic mix of SONET self-healing rings and other architectures that satisfy demand and protection requirements. Use of this software system by the Bellcore client companies has saved 10 to 30 percent in costs and orders of magnitude in time.
This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is-done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing-channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here Was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell. Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were. typical.
A program that produces single-layer planar routing over the cells for I2L and LST2L logic arrays is described. This router has been integrated into a layout system which was previously restricted to the layout of standard cell LSI chips. When used in conjunction with a channel router, the complete routing is produced automatically. This paper defines the over-the-cell routing problem, describes the algorithms for its solution, and presents typical routing results.
LTX is a minicomputer-based design system for largescale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc.In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.
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