We present an anomalous latchup failure phenomenon related to the large Nwell resistor associated with the generic RC-triggered, MOSFET-based Active Clamp circuit for on-chip ESD protection between VCC and VSS buses. A novel Active Clamp circuit with PMOS feedback technique has been proposed to reduce the IC's susceptibility to Latchup during negative current injection at neighboring 1 1 0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The effectiveness of this new Active Clamp circuit is confirmed by our experiment and simulation results.
Ah.ftracl -We p resent un unomll]OUS llltchup 1:1ilure phellllmenon related to the large Nwcll resistor associated with the gcnerie RC -triggered. MOSFET -based Active Clamp cireui! for on-chip ESD protection between VCC and VSS hus�s. 1\ nm'el Active Clamp circuit with PMOS fecdback tcchnique has been proposed to reduce the Ie's 'lI,ccptihilit�· tll Latchup during negativc current injection at ncig.hboring 1/0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The cffccti\'eness of this ncw Actiyc Chlmp circuit is contirmed b�' our e"periment and simulation results, Optimisation of tllc size of the PMOS feedback transistor is also discussed in thi,; pa p er.
Experimental results show ESD level will become worse if more I/O pins are connected to the ground during I/O to I/O ESD zapping for the substrate pumped Bus Switch ICs. As a result, it will fail +1KV during I/O to all other I/Os HBM ESD zapping configuration. A new substrate-triggered ESD protection structure is proposed to increase the ESD robustness of this special bus switch product. The test results show the IC with this new ESD protection structure can pass +3kV HBM ESD test.
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