Active ESD shunt with transistor feedback to reduce latchup susceptibility or false triggering

Abstract

We present an anomalous latchup failure phenomenon related to the large Nwell resistor associated with the generic RC-triggered, MOSFET-based Active Clamp circuit for on-chip ESD protection between VCC and VSS buses. A novel Active Clamp circuit with PMOS feedback technique has been proposed to reduce the IC's susceptibility to Latchup during negative current injection at neighboring 1 1 0 pads or false triggering of the RC trigger circuit due to noise on the VCC power line. The effectiveness of this new Active Clamp circuit is confirmed by our experiment and simulation results.

A novel ESD power supply clamp circuit with double pull-down paths

“…There are several main methods to implement delay elements: the separate RC network [4], the large resistance to pull down V gate [5], the feedback network [6][7][8][9][10][11], the flip-flop [12] and latch-up-like network [13]. The separate RC network occupies too much layout area, so it is seldom used now.…”

The Effect of IEC-Like Fast Transients on <formula formulatype="inline"><tex Notation="TeX">$RC$</tex> </formula>-Triggered ESD Power Clamps

“…The modified powerrail ESD clamp circuit incorporated with PMOS feedback, as shown in Fig. 1(b), was developed to mitigate such a mistrigger problem [9]. The transistor MPFB can help to keep the ESDclamping NMOS off during the normal power-up condition.…”