A very-high-performance HDTV image sensor is presented. The device tackles successfully a few typical "HDTV challenges": the very high RC values of the CCD gates are drastically lowered by means of a new interconnect scheme; a dual horizontal output register is used to lower the output rate; the device is provided with an output amplifier characterized by low noise, high bandwidth, and high conversion efficiency; and finally the imager is designed with a very compact and efficient image cell, providing the functions of photo-conversion, charge transport, highlight handling, charge resetting, and charge pumping. Compared to the competition, an imager with a high resolution, no smear when used in a professional camera, no image lag, simple charge-reset method or electronic shutter, and a high pixel uniformity with a fully linear response has been realized. 2304 samples I 1920 samoles 384 samde4 I I 5.33 psec' 26.67 p e c I 32 usec I Fig. 1. Schematic illustration of the different parameters defined by the Eureka HDTV standard.
A new double polysilicon gate technology for an 835 Kbit CCD video memory with a cell of 4x4 µm2 [1] is presented. The spacer technology for the LDD MOSFET's is integrated in the isolation of the double poly CCD structure. This makes the CCD fully compatible with standard CMOS processing and relaxes the anisotropic plasma etching of second poly electrodes. The charge transfer efficiency is high for a SCCD without fat zero (ε ≈ 2.10-4). Measurements and calculations on the charge transfer show no degradation for doping concentrations below 8.1015 cm-3. The leakage current density is measured on the 835 Kbit memory and agrees with earlier measurements on a 308 Kbit CCD video memory [2,6]
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