Surface impact ionization in silicon devices

Slotboom, J.W.; Streutker, G.; Davids, G.J.T.; Hartog, P.B.

doi:10.1109/iedm.1987.191468

Cited by 62 publications

(11 citation statements)

References 1 publication

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“…6. Impact ionization rate extracted from the anomalous gate current peak of the SOI MESFET (solid circles), compared with the previous data sets [25]- [27]. The solid line is a fit to the data using the Chynoweth model [28].…”

Section: Impact Ionization Ratementioning

confidence: 99%

“…The results from this brief are shown in Fig. 6 and compared with three data sets commonly cited in the literature [25]- [27]. A value for the channel doping N D = 7 × 10 16 cm −3 was chosen to get the best fit to the earlier data and is similar to values used for the numerical simulations of SOI MESFETs at the 350-nm node [12].…”

Section: Impact Ionization Ratementioning

confidence: 99%

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Impact Ionization in SOI MESFETs at the 32-nm Node

Thornton

Lepkowski

Wilk

2016

IEEE Trans. Electron Devices

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Silicon metal-semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, α, which agrees with three earlier data sets over nearly four orders of magnitude.Index Terms-Impact ionization, metal-semiconductor FETs (MESFETs), partially depleted (PD), Schottky junction, silicon-on-insulator (SOI).

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Section: Impact Ionization Ratementioning

confidence: 99%

Section: Impact Ionization Ratementioning

confidence: 99%

Impact Ionization in SOI MESFETs at the 32-nm Node

Thornton

Lepkowski

Wilk

2016

IEEE Trans. Electron Devices

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“…This phenomenon is important for devices with a narrow peak in the electric field distribution. Reference [10] gives a suitable formulation of the effective electrical field with the energy relaxation length taken into account. This effective field can be calculated by performing postprocessing on the numerical solution found for the Poisson and continuity equations, Therefore, once the electric field is known, we can calculate …”

Section: Implementation Of the Avalanche Effectmentioning

confidence: 99%

“…Since we are only interested in the variation of and , we calculate the total differential and eliminate ). Doing so, we obtain (10) Plotting lines of constant and using (10) (Fig. 8) and comparing results with lines of constant IP3 calculated using MAIDS with harmonic balance (Fig.…”

Section: Intermodulation Distortion and Optimum Bias Conditionsmentioning

confidence: 99%

Bipolar transistor epilayer design using the MAIDS mixed-level simulator

Vreede

Graaff

Willemen

et al. 1999

IEEE J. Solid-State Circuits

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Abstract-In this paper, we address the epilayer design of the bipolar transistor using the one-dimensional (1-D) mixed-level simulator MAIDS (microwave active integral device simulator). MAIDS facilitates simulation of the electrical behavior of bipolar (hetero) junction transistors with various doping profiles and under different signal conditions in a realistic circuit environment. MAIDS as implemented within Hewlett Packard's microwave design system is a useful and promising tool in the development of bipolar transistors for large-signal conditions. Using MAIDS, we have identified the dominant bipolar transistor distortion sources with respect to the biasing conditions. Simulation results are compared with small-and large-signal measurements for the BFQ135 transistor, which has been developed for cable television (CATV) applications. By analyzing the measured and simulated data, we have developed an optimum epilayer design map for third-order intermodulation distortion that has proven to be particularly useful in the epilayer dimensioning of transistors for CATV applications.

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“…where A = 2.45 × 10 -6 cm -1 and E ii = 1.92 × 10 6 V/cm have been determined for electrons at the silicon surface [15].…”

Section: B Transport Modelmentioning

confidence: 99%

Fast physical models for LDMOS power transistor characterization

Everett

Kearney

Johnson³

et al. 2011

2011 IEEE MTT-S International Microwave Symposium

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-A new quasi-two-dimensional (Q2D) model is described for microwave laterally diffused MOS (LDMOS) power transistors. A set of one-dimensional energy transport equations are solved across a two-dimensional cross-section in a "current-driven" form. This process-oriented nonlinear model accounts for thermal effects, avalanche breakdown and gate conduction. It accurately predicts DC and microwave characteristics as demonstrated by comparison with measured DC characteristics, transconductance, forward gain, S 21 , and large-signal gate and drain charges for a LDMOS transistor. The model is fast, taking less than 30 ms to extract a 50 point DC I DS -V DS characteristic and less than 5 ms to produce S-parameters at a single frequency.Index Terms -Field Effect transistor (FET), laterally diffused MOS (LDMOS), quasi-two-dimensional (Q2D), transistor model.

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Surface impact ionization in silicon devices

Cited by 62 publications

References 1 publication

Impact Ionization in SOI MESFETs at the 32-nm Node

Impact Ionization in SOI MESFETs at the 32-nm Node

Bipolar transistor epilayer design using the MAIDS mixed-level simulator

Fast physical models for LDMOS power transistor characterization

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