Cmos Technology for CCD Video Memories

Abstract

A new double polysilicon gate technology for an 835 Kbit CCD video memory with a cell of 4x4 µm2 [1] is presented. The spacer technology for the LDD MOSFET's is integrated in the isolation of the double poly CCD structure. This makes the CCD fully compatible with standard CMOS processing and relaxes the anisotropic plasma etching of second poly electrodes. The charge transfer efficiency is high for a SCCD without fat zero (ε ≈ 2.10-4). Measurements and calculations on the charge transfer show no degradation for doping concentrations below 8.1015 cm-3. The leakage current density is measured on the 835 Kbit memory and agrees with earlier measurements on a 308 Kbit CCD video memory [2,6]