This paper highlights the use of nanoprobing as a crucial and fast methodology for failure analysis (FA) in sub 20nm with an improved semi-auto nanoprobing system. Nanoprobing has the capability to localize as well as characterize the electrical behavior of the malfunctioning device for a better understanding of the failure mechanism. It provides a valuable guide to choose a proper physical FA technique to identify the root cause of the failure. This established methodology helps to accelerate the FA turnaround time and improve the success rate. Its application to a few of the front end of line and one back end of line issues is highlighted in the paper.
With a focus on open failure candidates, an extra effort in defining the ease of physical failure analysis (PFA) processing is taken in this paper by closely modeling the PFA processing flow and detailed estimation of the processing cost involved in every step is made. The paper begins with a discussion on the general PFA procedure to process open failure candidates in logic circuits. This is followed by a section that reviews common practice in PFA candidate selection, before proposing the comprehensive selection flow that aims to filter out the easiest candidate in terms of processing cost. This methodology is then evaluated by several case studies and is followed by a discussion on the potential future work. Case studies show that the cost model closely matches with real-world PFA turnaround time and the authors are working toward automating the full flow in software to further improve the efficiency.
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