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This paper presents a 4-Mh Phase-Change Memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-pm CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MBls, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone Phase-Change Memory with standard CMOS fabrication process.

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