4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

Bedeschi, F.; Bez, R.; Boffino, C.; Bonizzoni, Edoardo; Buda, E.; Casagrande, G.; Costa, L.; Ferraro, Marco; Gastaldi, R.; Khouri, O.; Ottogalli, F.; Pellizzer, F.; Pirovano, A.; Resta, Claudio; Torelli, G.; Tosi, M.

doi:10.1109/jssc.2005.847531

Cited by 50 publications

(24 citation statements)

References 10 publications

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“…The excellent programming characteristics and scalability of PCM make it a promising candidate for replacement of conventional technologies such as FLASH [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

Rajendran

Breitwisch

Lee

et al. 2009

IEEE Electron Device Lett.

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The resistance of phase-change-memory (PCM) cells measured during RESET programming (dynamic resistance, R d ) is found to be inversely proportional to the amplitude of the programming current, as R d = [A/I] + B. We show that parameters A and B are related to the intrinsic properties of the memory cell, and demonstrate by means of experimental data that they could be used to characterize the cell-to-cell process-induced variability of PCM cells.Index Terms-Chalcogenide, electrothermal simulations, nonvolatile memory, phase-change memory (PCM).

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“…The excellent programming characteristics and scalability of PCM make it a promising candidate for replacement of conventional technologies such as FLASH [2], [3].…”

Section: Introductionmentioning

confidence: 99%

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

Rajendran

Breitwisch

Lee

et al. 2009

IEEE Electron Device Lett.

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“…In this work we use 4-Mbit PCM test-chips produced by STMicroelectronics (Agrate , Italy) (see [8] and [9] for details). Fig.…”

Section: Phase Change Memoriesmentioning

confidence: 99%

“…The circuit used for the reading operation is schematically represented in Fig. I(b) [8,9]: M 1 is the bit-line (BL) selector nMOS and M 2 is the word-line (WL) selector nMOS. During the reading operation, VI and V 3 are high (>3V) and V 2 is set at 0.9V, assuring that the current flowing through a RESET cell is enough to be sensed by the external circuitry.…”

Section: Top Contactmentioning

confidence: 99%

Total Ionizing Dose effects on 4Mbit Phase Change Memory arrays

Gasperin

Wrachien

Cester

et al. 2007

2007 9th European Conference on Radiation and Its Effects on Components and Systems

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We investigate Total Ionizing Dose effects on 4Mbit Phase Change Memories (PCM) arrays. We demonstrate a high robustness of PCM against ionizing radiation. We irradiated PCM with 8-MeV electrons. Only small variations are measured in the cell distributions after irradiation. The primary cause of these variations is the degradation of the Bit-Line and the WordLine selection MOSFETs. Finally, radiation does not compromise the functionality of the SET and the RESET operations.

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“…Compared with the one-bipolar-junction-transistor-andone-resistor (1B1R) [15] and one-diode-and-one-resistor (1D1R) [16,17] structured memory cell, the one-transistorand-one resistor (1T1R) [18][19][20] memory cell is the simplest and the best compatible in process, in which only additional 2-3 masks accomplishing the chip integration though the cell size of 1T1R structure is larger than that of the 1B1R and 1D1R structures. In our previous work, an 8-Mb PCRAM experimental chip has been fabricated in a 130-nm 4-metal level standard CMOS technology [18].…”

Section: Introductionmentioning

confidence: 99%

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

et al. 2015

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In this letter, a phase change random access memory (PCRAM) chip based on Ti 0.4 Sb 2 Te 3 alloy material was fabricated in a 40-nm 4-metal level complementary metal-oxide semiconductor (CMOS) technology. The phase change resistor was then integrated after CMOS logic fabrication. The PCRAM was successfully embedded without changing any logic device and process, in which 1.1 V negative-channel metal-oxide semiconductor device was used as the memory cell selector. The currents and the time of SET and RESET operations were found to be 0.2 and 0.5 mA, 100 and 10 ns, respectively. The high speed performance of this chip may highlight the design advantages in many embedded applications.

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4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

Cited by 50 publications

References 10 publications

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

Total Ionizing Dose effects on 4Mbit Phase Change Memory arrays

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

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4-Mb MOSFET-selected /spl mu/trench phase-change memory experimental chip

Cited by 50 publications

References 10 publications

Dynamic Resistance&#x2014;A Metric for Variability Characterization of Phase-Change Memory

Dynamic Resistance&#x2014;A Metric for Variability Characterization of Phase-Change Memory

Total Ionizing Dose effects on 4Mbit Phase Change Memory arrays

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

Contact Info

Product

Resources

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Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory

Dynamic Resistance—A Metric for Variability Characterization of Phase-Change Memory