High-speed digital and wireless devices radiate unintentional electromagnetic noise, which can affect the normal operation of other devices within the same system, causing intrasystem electromagnetic interference (EMI) problems, or contribute to the total radiated EMI from the system, resulting in potential system-level EMI issues. PCB and system level shielding may alleviate the system-level EMI between wireless PCB board and the outside environment, but seldom prevent the intra-system EMI within the shielding enclosure. Package and System in Package (SiP) level shielding is desirable to shield the unintended radiation and protect the other circuits on board. Traditionally an external metal lid is employed to isolate the radiation from an IC, but the package cost and the size penalty due to the solder pads for shield attachment make the solution unattractive. In this paper, a new shielding technology for IC packages based on metal spray coating (conformal shielding) is presented. By spraying a conductive material on the sides of the package, a very thin metal layer is constructed around the top and four sides of a package. This very thin sprayed metal layer adds zero penalty to the package size and works similar to a solid metal shielding with very good shielding effectiveness; hence, it is suitable for wireless infrastructure, tele-communications, and high-speed digital applications.
In this paper, development of wafer level fan-out (WLFO) technology using ajinomoto build-up film (ABF) substrate with laser ablation process is introduced for low cost and high electrical performance for millimeter wave application. Wafer level fan-out (WLFO) technology using ABF substrate can enhance routing density and provide smaller form factor with lower parasitic elements than flip-chip chip scale packages (FCCSP). Moreover, short electrical paths from die out to package out can be realized with WLFO, and the low-k ABF material provides good electrical properties for high frequency areas. In this paper, the process of WLFO using ABF substrate with laser drilling is explained and electrical parasitic elements are compared between FCCSP and WLFO using 3D simulation tools. In addition, electrical characterization of coplanar waveguide (CPW) structure and interconnection models from die I/O pad to balls using 3D EM simulation are conducted to estimate effectiveness on millimeter wave range. Actual measurements of CPW structures are also presented.
There are 2 primary drivers for advanced substrate technologies to support the next generation of products. One driver is silicon designs which are shifting to 20–40 GBit applications. The band width of these products are requiring advanced materials, and designs which use much thinner cores making routing and manufacturing of these packages easier. The second driver is the move more advanced silicon nodes which also drives the importance for much better power delivery. Coreless substrates enable both of these applications by eliminating the core layer which enables much finner via pitchs to route signals and power/gnd planes. The thinness also reduces the bandwidth used up by the substrate which also enables better electrical performance. This paper will focus on the electrical drivers including simulation to support the structure, flip chip assembly of the package as well as the reliability data associated with the assembly.
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