In this work, die stresses in wire bonded chipon-board (COB) packages have been measured using special (111) silicon stress test chips. The test die incorporate an array of optimized eight-element dual polarity piezoresistive sensor rosettes, which are uniquely capable of evaluating the complete stress state (six stress components) at points on the surface of the die. Sensor resistance measurements were recorded before packaging, after die attachment, and throughout the encapsulant cure process. Using the appropriate theoretical equations, the stresses at sites on the die surface have been calculated from the raw sensor resistance data. Also, three-dimensional (3-D) nonlinear finite element simulations of the chip-on-board packages were performed, and the stress predictions were correlated with the experimental test chip data.
This paper demonstrates the use of special test chips containing arrays of CMOS FET differential pairs as mechanical stress sensors and reports the first results of measurements of packaging induced die stresses for temperatures ranging from the epoxy cure temperature (430K) to near liquid nitrogen temperature (90K). The experimental test chip consists of 49 CMOS stress sensor rosettes distributed across the die and interconnected by a novel scheme.
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