Complete stress state measurements in chip on board packages

Zou, Yida; Suhling, Jeffrey C.; Johnson, Richard W.; Jaeger, R.C.

doi:10.1109/icmcm.1998.670816

Cited by 9 publications

(6 citation statements)

References 8 publications

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“…The scaling parameter 0" 0 and the Weibull modulus m should be measured. F,,, , (0", H -ex{ -�Aff m,.,", ( �: n (5) Up to now, the scaling parameter and the Weibull modulus have been assumed as valid for the whole chip. Then, the highest risk of chip is given directly at the upper chip edges.…”

Section: Measurement Stressmentioning

confidence: 99%

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New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

Steiert

Wilde

2014

2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and

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Due to increased demands, reliability has become an important part of the research and development on electronics, in the last years. An important reliability factor is failure due to chip fracture. Tn several scientific papers three types of chip fracture are described: vertical cracks, horizontal cracks and mixed cracks. Till now, all approaches to explain the relations of these crack types have based on the deterministic fracture mechanics. But especially for statistical process control, it is better to use a probabilistic fracture mechanic based on the Weibull distribution.In the present work damages caused by the dicing were analyzed by means of SE M-pictures. A special type of crack was found. Such cracks have a preferred orientation which is parallel to the dicing feet direction. The influence of those cracks on the breaking strength of silicon chips was investigated. The results showed a kind of dicing caused anisotropic breaking strength. This means the fracture relevant die strength depends on the local orientation of the stresses which acts on the chips. To detail this phenomenon a new equivalent stress was develop, which offers to directly compare stresses by means of theirs impact to fracture.

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Section: Measurement Stressmentioning

confidence: 99%

“…Many investigations were performed in order to find out to which kind and level of stresses chips are exposed in electronic components [4][5][6][7] . An overview of previous investigations points out that typical die stresses are in the range of ±50 MPa up to ±200 MPa.…”

Section: Introductionmentioning

confidence: 99%

New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

Steiert

Wilde

2014

2014 15th International Conference on Thermal, Mechanical and Mulit-Physics Simulation and Experiments in Microelectronics and

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show abstract

“…Similar stress distributions on the surface of the die were found for these two adhesives because they share similar mechanical properties, curing conditions, etc. Also, the magnitudes of the normal stress difference values for these adhesives were found to he considerably higher than those found for more conventional die attachment materials [4,5]. The stress magnitudes were lower for the other three die attachment materials, even though the CTE's of adhesives C, D, E are larger than those of adhesive A, B, and F. This is because adhesives A, B, and F have higher elastic moduli, higher glass transition temperatures, and higher curing The experimental results for adhesives A and B have been also evaluated through correlation with the predictions of preliminary three-dimensional finite element simulations of the packaging process.…”

Section: Die Stress Measurementmentioning

confidence: 66%

“…The room temperature sensor resistances were then measured, and the stresses were calculated using the original (wafer level) and final (packaged) die sensor resistances, and eqs. (3,4). Since both of these resistor measurements and the calibration of the piezoresistive coefficients were done at room temperature (23OC), any thermal errors will be minimized.…”

Section: Die Stress Measurementmentioning

confidence: 99%

“…They considered four substrate materials: alumina, tungstedcopper alloy, molybdenum, and copper. Zou, et al [4,5] have measured three-dimensional die attachment stresses in chip on board and 240 pin Quad Flat Pack (QFP) packages using (1 11) silicon test chips. In these studies, the magnitudes of the die attachment stresses were shown to be fairly low (under 10 MPa), and were found to he much lower than the stresses induced by encapsulation).…”

Section: Introductionmentioning

confidence: 99%

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Die surface stress variation during thermal cycling and thermal aging reliability tests

Zou

Suhling

Jaeger

et al.

1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299)

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In this work, the variation of die stress during thermal cycling and thermal aging reliability tests has been explored experimentally. Special (1 11) silicon stress test chips containing an array of piezoresistive sensor rosettes have been applied within 281-pin ceramic Pin Grid Array (PGA) packages. The test die contained optimized eight element dual polarity rosettes, which are uniquely capable of evaluating the complete stress state at points on the surface of the die. Calibrated and characterized test chips were attached to the PGA packages using six high temperature die attachment adhesives designed for avionic applications. The adhesive systems included silver filled glasses, polyimide pastes, thermoplastic films, and gold germanium adhesives. The resistances of the sensors were recorded at room temperature before and after die attachment. The induced thermal stresses at sites on the die surface have been calculated using the measured resistance changes and piezoresistive theory. A comparison of the room temperature die stresses caused by the different die-attachment materials has been made. The stresses on the die surface after packaging were also characterized as a function of temperature. After the initial stress measurements, thermal aging and thermal cycling tests were conducted on the packages. The various die attachment materials were further evaluated by observing the changes in stress that occurred during these reliability tests. Finally, three-dimensional finite element simulations of the PGA packages were performed, and the stress predictions were correlated with the experimental test chip data. 0-7803-5231 -9/99/$10.00 81 999 IEEE

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Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages

Zou

Suhling²,

Jaeger³

et al.

1998 Proceedings. 48th Electronic Components and Technology Conference (Cat. No.98CH36206)

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Complete stress state measurements in chip on board packages

Cited by 9 publications

References 8 publications

New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

New equivalent stress describes the dicing caused anisotropic breaking strength of silicon dies

Die surface stress variation during thermal cycling and thermal aging reliability tests

Three dimensional die surface stress measurements in delaminated and non-delaminated plastic packages

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