The unitarizable irreps of the deformed para-Bose superalgebra pB,, which is isomorphic to Uq[osp(l/2)], are classified at q being root of 1. New finite-dimensional irreps of U,[osp(l/2)1 are found. Explicit expressions for the maIrix elements are written down.
Silicon selective epitaxial growth using the SiH2Cl2–HCl–H2 system was successfully accomplished on a window surrounded by fine patterned insulator films as a mask. Surface planarity was obtained at less than 80 Torr reduced pressure. Good selectivity was realized by suitable HCl injection during epitaxial growth. Moreover, it was found that the induced defect density on the epi-layer was less at lower growth temperature.
In selective epitaxy, growth rate is modified by the ratio of unmasked area to entire surface area and by each window area on a wafer. Such “local loading effect” phenomena were studied in a SiH2Cl2/HCl/H2 selective epitaxial growth system. The effect is attributed to species spatial concentration variation which is generated by coexistence of a masked area and windows on a wafer. The growth condition which can suppress the effect is obtained for VLSI device fabrication.
An advanced bulk CMOS process has been developed using SEG (Selective Epitaxial Growth) isolation technique and high impurity concentration substrate, in order to suppress latch-up phenomenon. CMOS devices are fabricated on epitiaxial layer, which is selectively grown over p-type silicon substrate surrounded by a 2 p m t h i c k Si02 insulator, using a reduced pressure SiH2C12-H2-HCI system. P-channel devices are formed in an n-well, having 3 pm depth. The gate oxide is 20 nm thick. 400 nm thick phosphorus-doped polysilicon is used as a g a t e electrode. The transition region for autodoping from p+-s u b s t r a t e to the epitaxial layer is less than 1 pm. This isolation combined with low resistivity substrate is e f f e c t i v e to reduce latch-up for CMOS circuits. Submicron gate CMOS operation is confirmed using SEG isolation technique.
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