The need for the high-speed analogue-to-digital converters demands the use of regenerative comparators. The strong positive feedback present in the regenerative comparators helps the comparator to work efficiently at the high-speed operations. This work proposes a low power auxiliary circuit to improve the high-frequency performance of the comparator. The proposed architecture along with the conventional comparators is simulated in 65-nm complementary metal oxide semiconductor (CMOS) technology with a supply voltage of 0.9 V. The maximum operating frequency of the proposed comparator is 6.25 GHz for a differential input voltage of 1 mV.
To meet the ever increasing demand for transferring image and video data in present day communication system without compromising the speed, either the channel bandwidth has to be increased or the total data traffic has to be decreased. As small screen devices and chat applications do not need original quality images to be reconstructed, certain relaxation on the quality of image is allowed if the total data traffic can be reduced to a great extent. Due to this reducing the size of the image to be sent by transforming it to a sparse domain, followed by decoding to retain the required quality has emerged as a solution. Verilog implementation of the proposed algorithm gives permission to the user to set the quality of the image to be reconstructed (by defining PSNR value) and allows the user to set the required compression by assigning the value of bits per pixel(bpp).
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