6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process

Kala, Siddharth Rajkumar; Chandaka, Sushma; B, Nithin Kumar Y.; Harishchandra, Vasantha Moodabettu; Bonizzoni, Edoardo

doi:10.1049/iet-cds.2019.0421

Cited by 7 publications

(2 citation statements)

References 28 publications

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“…There are various types of ADCs that has been grouped according to its conversion architecture such as Flash ADC, SAR ADC, and pipelined ADC etc. Each ADC is designed according to its characteristics that help to determine for what application it is suitable [29], [31]- [34]. Here, Flash ADC is designed with the help of clocked comparator.…”

Section: Flash Adc Architecture Using Proposed Dynamic Comparatormentioning

confidence: 99%

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Yadav

Wairya

2022

Preprint

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An ultimate requirement of the less power, high speed and energy efficient analog to digital converters (ADCs) have given immense popularity to dual stage positive feedback based dynamic regenerative clocked comparators. In this paper, a dynamic comparator based on shared charge logic is proposed. The latch of the proposed comparator uses a PMOS transistor, which greatly reduces delay and power consumption. This, design can operate at maximum frequency of 2GHz at supply voltage of 0.8V. This circuit is designed with CMOS 90nm and 45-nm technology along with implementation in CNTFET 10-nm technology. The proposed architecture consumes power of 3.3 µW and delay of 58.4ps at 0.8V supply voltage, 5mV input difference voltage, 0.7V common mode voltage. The power consumption is 81.4% less when compared with CNTFET based proposed architecture. Thus, CNTFET technology is proving to be power efficient and can operate at supply voltage as low as 0.4V.The Monte Carlo simulation of proposed architecture for power, delay, PDP and energy efficiency is also demonstrated in this paper along with process corner analysis. Monte Carlo simulations for mismatch analysis and input offset voltage for proposed comparator are done. Mathematical analysis is done for the delay of the proposed comparator. A high performing 3-bit Flash ADC architecture is implemented using proposed dynamic comparator. This Flash ADC architecture is simulated on 90nm technology which results in large reduction in static power consumption.

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Section: Flash Adc Architecture Using Proposed Dynamic Comparatormentioning

confidence: 99%

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Yadav

Wairya

2022

Preprint

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“…In [1,[8][9][10][11][12][13][14] and [26][27][28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1].…”

mentioning

confidence: 99%

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

Krishna,

Nambath

2024

Microelectronics Journal

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6.25 GHz, 1 mV input resolution auxiliary circuit assisted comparator in 65 nm CMOS process

Cited by 7 publications

References 28 publications

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

Performance and Design analysis of High Speed Charge Shared Dynamic Comparator for ADC Architecture in VLSI Application

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

High-speed cascode cross-coupled CMOS dynamic comparator with auxiliary inverter pair

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