A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

Kadhao, Rupesh D.; Rajan, Siddharth; B, Nithin Kumar Y.; Vasantha, M. H.; Dwivedi, Devesh

doi:10.1109/vlsid57277.2023.00036

2023 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems (VLSID) 2023

DOI: 10.1109/vlsid57277.2023.00036

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A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

Rupesh D. Kadhao

Siddharth Rajan

Nithin Kumar Y. B

et al.

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A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process

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References 26 publications

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