No abstract

Major challenges concerning the reliability of resistive switching random access memories based on the valence change mechanism (VCM) are short-term instability and long-term retention failure of the programmed resistance state, particularly in the high resistive state. On the one hand, read noise limits the reliability of VCMs via comparatively small current jumps especially when looking at the statistics of millions of cells that are needed for industrial applications. Additionally, shaping algorithms aiming for an enlargement of the read window are observed to have no lasting effect. On the other hand, long-term retention failures limiting the lifetime of the programmed resistance states need to be overcome. The physical origin of these phenomena is still under debate and needs to be understood much better. In this work, we present a three-dimensional kinetic Monte Carlo simulation model where we implemented diffusion-limiting domains to the oxide layer of the VCM cell. We demonstrate that our model can explain both instability and retention failure consistently by the same physical processes. Further, we find that the random diffusion of oxygen vacancies plays an important role regarding the reliability of VCMs and can explain instability phenomena as the shaping failure as well as the long-term retention failure in our model. Additionally, the results of the simulations are compared with experimental data of read noise and retention investigations on ZrO2-based VCM devices.

No abstract

In this work, we experimentally characterize the endurance of 2 Mbit resistive switching random access memories (ReRAMs) from a 16 MBit test-chip. Here, very rare failure events where the memory cells become stuck in the low-resistive state (LRS) are observed. As this failure mechanism is the limiting one concerning the endurance of this ReRAM implementation, extensive investigations are conducted and presented. The experimental findings are detailed via a voltage divider model, illustrating why memory cells can become stuck in the LRS. It is proposed, that an insufficient voltage dropping over the cell due to an unfavorable combination of cell-and transistor resistances is responsible for stuck-at-LRS bits. Furthermore, we give predictions for the origin of these suboptimal combinations. Additionally, a onedimensional Kinetic Monte Carlo (KMC) model that allows a statistical investigation of large numbers of cells with regard to rare random events has been developed. Here, we fortify our proposed explanation for the observed failure mechanism by the simulation and evaluation of the switching process of the memory. All simulations are in very good agreement with the experimental data. Finally, based on our findings, we give suggestions for the improvement of switching algorithms.