Numerous publications have highlighted the advantages of redox based resistive switching memories (ReRAM), being e.g., fast switching speed, low energy consumption, high scalability and cost‐effective fabrication. Approaching their application in commercial memory chips, the research focus shifts more and more towards understanding and optimizing different aspects of reliability. Here, it is vital to account for the statistics in large memory blocks, as certain failure mechanisms are observed to only affect few bits per million and thus cannot be investigated with single devices. In a cooperation of RWTH Aachen and Infineon Technologies, we comprehensively studied the variability, retention, and endurance of filamentary valence change memory (VCM), integrated into 28 nm CMOS on Mbit scale. This paper reviews the main findings of this project. Throughout the cooperation, it was found that the programmed states follow characteristic statistics, where the low resistive state (LRS) is normally distributed and the high resistive state (HRS) follows log‐normal statistics. These intrinsic statistics were found to be based on a dynamic equilibrium in the random walk of oxygen vacancies in the switching layer, which can be experimentally observed as characteristic read noise or short term instability. On long timescales, these statistics are remarkably stable, providing a high data retention. However, the existing long‐term degradation can be characterized by shifting and broadening of the originally programmed HRS resistance distributions. This emphasizes that a reliable assessment of the data retention is only possible with a statistical analysis. Lastly, a high endurance of more than 500 k cycles was demonstrated on the Mbit scale. Whereas most devices switch reliably beyond this mark, a tail of few devices appears to fail resetting. However, devices which become stuck in the LRS can be recovered by further RESET attempts and no permanent failures were observed. Using compact kinetic Monte Carlo modeling, the interplay of access transistor and ReRAM cell has been identified as the origin of this failure. In rare cases the voltage divider of these two elements leads to insufficient voltage over the ReRAM cell resulting in a failed attempt. In conclusion, the reviewed results of our cooperation provide a comprehensive understanding of the key reliability aspects, variability, retention and endurance, laying a solid foundation for a successful commercial application of CMOS integrated VCM ReRAM.This article is protected by copyright. All rights reserved.