In this paper, we will propose an innovative DFM (Design for Manufacturability) design flow. This flow achieves designs for logic products that are much more manufacturable than those using traditional design flows in nanometer technologies. The proposed DFM design flow is unique because it integrates manufacturability informationextracted directly from the target nanometer process-into the timing-driven synthesis and P&R cost function. As such, the designer is able to easily analyze optimal die size, yield, and performance trade-offs and seamlessly account for them before releasing the design to reticle creation. This proposed design flow system is comprised of three major elements:A DFM extension library, which creates "Yield Strength" variants of the basic logic functions in the library. 0A new design view data-file containing a precharacterized set of design attributes extracted from the cell library layouts and the required target process parameters extractions. A set of sofhare elements that plug the manufacturability information into the standard IC design creation and analysis flow.The EDA tools interact with these elements to determine the most manufacturable mapping and arrangement of any given logic function onto the physical library. The application of the proposed design flow in various 130nm designs will be presented. These will demonstrate the validity of the proposed approach, where DFM trade-offs are made early in a design effort, and will illustrate the practical advantages and implications of this approach in a nanometer design flow.
Power dissipation in digital circuits is strongly pattern dependent. Thus, to derive accurate simulation-based power estimates, a large amount of input vectors is usually required. This paper proposes a vector compaction technique aiming at providing accurate power figures in a shorter simulation time for complex sequential circuits characterized by some hundreds of inputs. From pair-wise spatio-temporal signal correlations, the proposed approach is based on bit clustering and temporal partitioning of the input stream aiming at preserving the statistical properties of the original stream and maintaining the typical switching behavior of the circuit. The effectiveness of the proposed approach has been demonstrated over a significant set of industrial case studies implemented in CMOS submicron technology. While achieving a 10x to 50x stream size reduction, the reported results show an average and maximum errors of 2.4% and 7.1% respectively, over the simulation-based power estimates derived from the original input stream
Mixed-swing logic employs multiple power supply rails and device threshold voltages and allows us to create richer cell libraries with a wider range of power/speed tradeoffs. However, mapping onto such a library with a conventional technology mapper will not exploit the full potential of a mixed-swing methodology. To remedy this, we have developed a new technology mapping tool that specifically targets mixedswing logic. Our approach combines (1) efficient clustering and clusterlevel delay budgeting for the uncommitted logic, with (2) an exhaustive search for the optimal cover that is rendered practical by the clustering process. Power savings up to 3X have been demonstrated with our mixedswing solutions versus single power supply implementations.
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