Monolithically integrating the energy supply unit on a silicon integrated circuit (IC) requires the development of a thin-film solid-state battery compatible with silicon IC fabrication methods, materials, and performance. We have envisioned materials that can be processed in a silicon fabrication environment, thus bringing local stored energy to silicon ICs. By incorporating the material directly onto the silicon wafer, the economic parallelism that silicon complementary metal-oxide-semiconductor (CMOS) technology has enjoyed can be brought to power incorporation in each IC on a processed wafer. It is natural to look first towards silicon CMOS materials, and ask which materials need enhancement, which need replacement, and which can be used “as is.” In this study, we begin by using two existing CMOS materials and one unconventional material for the construction of a source of electric power. We have explored the use of thermally grown silicon dioxide (SiO2) as thin as 9nm acting as an electrolyte material candidate in a solid-state power cell integrated on silicon. Other components of the thin-film cell consisted of rf-sputtered lithium cobalt oxide (LiCoO2) as the cathode and highly doped n-type polycrystalline silicon (polysilicon) grown by low-pressure chemical-vapor deposition as the anode. All structures were fabricated using conventional microelectronics fabrication technology. The charge and discharge behaviors of the LiCoO2∕SiO2∕polysilicon cells were studied. On the basis of the impedance measurements an equivalent circuit model of an ultrathin cell was inferred, and its microstructure was characterized by electron microscopy imaging. In spite of its high series resistance (∼4×107Ω), we have shown that an ultrathin layer of an as-deposited Li-free SiO2 is an interesting candidate for an electrolyte or controllable barrier layer in lithium-ion-based devices.
Effects of manganese oxide-mixed abrasive slurry on the tetraethyl orthosilicate oxide chemical mechanical polishing for planarization of interlayer dielectric film in the multilevel interconnection J. Vac. Sci. Technol. A 26, 996 (2008); 10.1116/1.2936225 Controlled chemical mechanical polishing of polysilicon and silicon dioxide for single-electron device Monolithic integration of different electronic circuit elements onto a single chip is beneficial for the purpose of reducing overall system cost as well as improving performance and reliability. Integrating a power unit onto a silicon chip requires the implementation of a thin-film solid-state battery that is compatible with existing silicon integrated circuit technology in terms of manufacturing methods, materials, and performance. One of the materials in the battery industry, studied by us, is silicon dioxide ͑SiO 2 ͒. The high level of process control for thin SiO 2 layers which is a result of microelectronic advances, its insulating properties, and its past reported permeability to light ions have motivated us to exploit SiO 2 as a solid-state electrolyte in our integrated thin-film battery. This SiO 2 electrolyte layer is thermally grown from an amorphous silicon ͑a-Si͒ thin layer deposited on doped polycrystalline silicon ͑polysilicon͒ which serves as the anode against a thin-film-sputtered LiCoO 2 cathode. We have fabricated and characterized ultrathin solid-state thin-film power cells consisting of LiCoO 2 , SiO 2 , and polysilicon. Cells containing an ultrathin SiO 2 lithium-free electrolyte with a thickness range of 7 -40 nm and active-area sizes of 5 ϫ 5, 2 ϫ 2, 1 ϫ 1, and 0.5ϫ 0.5 mm 2 were created using established microelectronics processing and expertise. Ultrathin cells require smooth surfaces ͑nanometer-scale roughness͒ as opposed to higher roughness encountered in bulk batteries and microbatteries. To ensure a very thin and flat electrolyte, this work demonstrates the implementation of a planarization step by using chemical mechanical polishing ͑CMP͒ in the fabrication of the integrated solid-state thin-film lithium-ion battery. Polishing the polysilicon layer reduced its 1 ϫ 1 m 2 root-mean-square roughness from 8.06 to 0.53 nm and led to smoother interfaces and to higher quality of the SiO 2 grown on top of it. The cells were charged and discharged using conventional microelectronic electrical testing equipment and exhibited improved performance when prepared with the additional CMP planarization step. Up to 40% of the charge was retrieved from the planarized cells compared to a maximum of 14.5% retrieved from the nonplanarized cells. The open circuit voltage ͑V OC ͒ of the LiCoO 2 / SiO 2 /polysilicon cell was estimated by comparing the initial charge voltage values obtained with different electrolyte thicknesses and was found to be 2.19± 0.02 V. The results presented in this work show the importance of interfacial quality in the process of moving to integrated power on a chip.
We report the creation of two novel complementary metal oxide semiconductor ͑CMOS͒-compatible platforms: strained-silicon on silicon ͑SSOS͒ and strained-silicon on silicon-germanium on silicon ͑SGOS͒. SSOS substrate has an epitaxially defined, strainedsilicon layer directly on silicon wafer without an intermediate SiGe or oxide layer. SSOS is a homochemical heterojunction, i.e., a heterojunction defined by strain state only and not by an accompanying compositional change. SGOS has an epitaxially defined SiGe layer between the strained-silicon channel and the Si substrate, which may prove necessary to prevent excessive off-state leakage in metal oxide semiconductor ͑MOS͒ devices due to overlap of source-drain contacts and the interfacial misfit array
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