A 2 V, 25 MS/s, current-mode and pipelined analog-todigital converter (ADC) which realizes a 1.5-bit bit-block architecture and uses a front-end current-mode sample-and-hold (S/H) circuit is described. In order to obtain the precise output current without suffering from poor current mismatch in a bitblock, the input and output currents in a current-mirror circuit are exchanged at every clock period. This produces signal currents at the output of a bit-block with positive and negative mismatch errors in turn. Since the analog-to-digital (A-D) converted digital codes of a bit-block contain these positive and negative mismatch errors, the errors are canceled out by taking the average of the consecutive digital codes at the output part of the ADC. A current-mode ADC using this proposed scheme has been fabricated by using 0.25 um CMOS devices. The results show that the effective number of bits (ENOB) is 7.6, that the spurious-free dynamic range (SFDR) is 48 dB, with a 20 MHz clock from a 2 V supply voltage.
Rapid nitridations of oxides were employed to suppress reaction of gate metals with oxides for a
TiSix‐normalpolycide/10 normalnm
thick oxide gate. Oxides were nitrided by a lamp‐heated rapid thermal annealer in dilute ammonia at 900°–1150°C for 15– 300s. Capacitance‐voltage and current‐field curves, and charge‐to‐breakdown
QBD
were measured. A slight nitridation only for 60s at 900°–950°C is enough to eliminate low field breakdowns observed for an oxide and to increase
QBD
by more than one order of magnitude. Further nitridations, however, lead to reduction of
QBD
. Advantages of short‐time annealing have been shown.
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