Increasing complexity of circuit boards and surface mount technology has made it difficult to test them using traditional in-circuit test techniques. A design-forAtestability framework has been proposed as the IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture. This architecture simplifies board test by providing an electronic bed of nails. It also provides access to other test features that may be present on a chip.Because of the serial nature of the tests that use BoundaryScan, it is important to minimize the test size while maintaining diagnosability. This has renewed interest in exploring efficient test algorithms and implementation techniques. This paper presents a new framework for analyzing the algorithms proposed for testing and diagnosing wiring interconnects. Using this framework, the algorithms proposed in the literature are analyzed, clearly identifying their capabilities and limitations. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented.
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