A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects

Abstract

Increasing complexity of circuit boards and surface mount technology has made it difficult to test them using traditional in-circuit test techniques. A design-forAtestability framework has been proposed as the IEEE Standard 1149.1, Test Access Port and Boundary-Scan Architecture. This architecture simplifies board test by providing an electronic bed of nails. It also provides access to other test features that may be present on a chip.Because of the serial nature of the tests that use BoundaryScan, it is important to minimize the test size while maintaining diagnosability. This has renewed interest in exploring efficient test algorithms and implementation techniques. This paper presents a new framework for analyzing the algorithms proposed for testing and diagnosing wiring interconnects. Using this framework, the algorithms proposed in the literature are analyzed, clearly identifying their capabilities and limitations. A new optimal adaptive algorithm that can reduce test and diagnosis complexity is also presented.

Automatic Test Pattern Generation for Interconnect Open Defects

“…Rodríguez-Montañés et al [14] proposed a diagnosis approach based on the relative values of voltages induced by interconnect opens and incorporating I DDQ data. Further literature is available on testing open defects in board interconnects which is not a target of our work [15,16].…”

BIST TPG for faults in system backplanes

“…Most previous work in testing interconnects focused on the development of deterministic tests for interconnect between chips at the board level [7,9,15,17,22,25,28]. As pointed out above, the extension of these board level methods to backplane testing is non-trivial.…”

Diagnosis of Wiring Networks: An Optimal Randomized Algorithm for Finding Connected Components of Unknown Graphs

“…It has applications to design and testing of very large scale integration (VLSI), multi-chip module (MCM) and printed circuit board (PCB) systems [2,3,4,5,8]. A wiring network consists of a set of nets, each having one driver and one receiver.…”

“…Garey, Johnson and So [3] observed that if we are given partial information about the edge set of G, then finding an optimal algorithm to test G = K n becomes NP-complete (reduction from chromatic number). For our problem of finding all connection classes, Jarwala and Yau [4] provided a heuristic using lg n + n − k queries, where k is the number of components. There is also a non-adaptive version of the problem where the inputs of all queries are decided before asking the oracle any question [2,8,9].…”