Built-in self-test: assuring system integrity

Konemann, B.; Bennetts, Ben; Jarwala, N.; Nadeau-Dostie, B.

doi:10.1109/2.544236

Cited by 13 publications

(4 citation statements)

References 7 publications

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“…At the same time system clock rates continue to rise and timing margins become narrower, therefore a test should also cover the dynamic properties of a circuit. Ideally, the test is performed at the nominal system clock rate (at-speed testing [37] [38]), which also helps to keep test duration low. With a conventional external test approach, however, non-idealities in contacts and wiring deteriorate signal quality substantially, which prohibits at-speed testing.…”

Section: Figure 59: Principle Of Built-in Self-test Fmentioning

confidence: 99%

“…Another crucial cost factor is the degree of automation: VLSI design tools automatically generate the set of test vectors, but the adaptation or design process for the tester hardware and probing remains an expensive requirement for the conventional testing approach. As opposed to that there are suites of tools available that automatically add a complete and largely optimized BIST environment to a VHDL or Verilog-design [38]. Table 5.I summarizes the above discussion on the benefits of BIST.…”

Section: Figure 59: Principle Of Built-in Self-test Fmentioning

confidence: 99%

“…BIST allows for optimal diagnostic resolution. The extra cost for system level BIST can be kept at a minimum, since a reuse of the factory BIST logic on chip level is possible [38].…”

Section: Bist and Hierarchical Testingmentioning

confidence: 99%

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Design for Testability and Built-In Self-Test

Fault Diagnosis of Analog Integrated Circuits

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Section: Figure 59: Principle Of Built-in Self-test Fmentioning

confidence: 99%

Section: Figure 59: Principle Of Built-in Self-test Fmentioning

confidence: 99%

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Design for Testability and Built-In Self-Test

Fault Diagnosis of Analog Integrated Circuits

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“…vector generation methods detect single-stuck faults; where the value of a line in the circuit is always at logic '1' or '0'.Test vectors are generated based on a model of the circuit and a given fault model. Test vector generation can be faultindependent or fault-oriented[46] [47]. In the fault-oriented process, the two fundamental steps in generating a test vector are to activate (or excite) the fault, and to propagate the resulting error to an observable output.…”

mentioning

confidence: 99%

Systematic testing of multicast routing protocols: analysis of forward and backward search techniques

Estrin

Gupta

Proceedings Ninth International Conference on Computer Communications and Networks (Cat.No.00EX440)

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Abstract-The recent growth of the Internet and its increased heterogeneity have increased the complexity of network protocol design and testing. In addition, the advent of multipoint (multicast-based) applications has introduced new challenges that are qualitatively different in nature than the traditional point-to-point protocols. Multipoint applications typically involve a group of participants simultaneously, and hence are inherently more complex. As more multipoint protocols are coming to life, the need for a systematic method to study and evaluate such protocols is becoming more apparent. Such method aims to expedite the protocol development cycle and improve protocol robustness and performance.In this paper, we present a new methodology for developing systematic and automatic test generation algorithms for multipoint protocols. These algorithms attempt to synthesize network topologies and sequences of events that stress the protocol's correctness or performance. This problem can be viewed as a domain-specific search problem that suffers from the state space explosion problem. One goal of this work is to circumvent the state space explosion problem utilizing knowledge of network and fault modeling, and multipoint protocols. The two approaches investigated in this study are based on forward and backward search techniques. We use an extended finite state machine (FSM) model of the protocol. The first algorithm uses forward search to perform reduced reachability analysis. Using domain-specific information for multicast routing over LANs, the algorithm complexity is reduced from exponential to polynomial in the number of routers. This approach, however, does not fully automate topology synthesis. The second algorithm, the fault-oriented test generation, uses backward search for topology synthesis and uses backtracking to generate event sequences instead of searching forward from initial states.Using these algorithms, we have conducted studies for correctness of the multicast routing protocol PIM. We propose to extend these algorithms to study end-to-end multipoint protocols using a virtual LAN that represents delays of the underlying multicast distribution tree.

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Using ATPG vectors for BIST test pattern generator

Asakawa

Iwasaki

2001

Systems & Computers in Japan

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SUMMARYAs a solution to improve the characteristics of pseudo-random pattern tests, a BIST-oriented test pattern generator (TPG) designed to achieve complete coverage of stuck-at faults with short test sequences is proposed. In the proposed method, ATPG vector sets are split-shifted to obtain pseudo-random vectors, and such vectors are then used in a mixed test pattern. Since random pattern resistant faults are detected by ATPG vectors, stuck-at faults can be covered completely with a short test sequence. This paper presents the proposed TPG configuration, test pattern generation algorithm, and the selection of the vector set for bit shift. The proposed method is evaluated in terms of test length and hardware overhead by applying it to ISCAS benchmark circuits. © 2001 Scripta Technica, Syst Comp Jpn, 32(11): 18, 2001

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Built-in self-test: assuring system integrity

Cited by 13 publications

References 7 publications

Design for Testability and Built-In Self-Test

Design for Testability and Built-In Self-Test

Systematic testing of multicast routing protocols: analysis of forward and backward search techniques

Using ATPG vectors for BIST test pattern generator

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