The design and characterization in high-voltage (HV)-CMOS technology of an innovative intelligent power switch (IPS) for harsh automotive applications is proposed in this paper. To safely handle the ordinary and extraordinary automotive electrical and environmental conditions, a systematic design flow is followed: several design solutions are presented at the architectural and circuital level, integrating on-chip self-diagnostic capabilities and full protection against the high voltage and reverse polarity, the effects of wiring parasitics, and the over-current and over-temperature phenomena. Moreover, the current slope and soft start integrated techniques ensure a low electromagnetic interference, and the IPS is also configurable to efficiently drive different interchangeable loads. The innovative IPS has been implemented in a 0.35-mu m HV-CMOS technology and has been embedded in mechatronic third generation brush-holder regulator system-on-chip for an automotive alternator. The electrical simulations and experimental characterization and the testing at component and on-board system levels prove that the proposed design allows a compact and smart power switch realization facing the harshest automotive conditions
Purpose
The sustainability of the Lean Six Sigma (LSS) program represents the most challenging aspect for most of the organizations dealing with this methodology. In this scenario, the purpose of this paper is the description of the AMSE (which stands for Assessment, Monitoring, Sustainability, Expansion) Model, that represents a leading-edge approach to implement an effective LSS deployment on a permanent basis, by means of a structured roadmap.
Design/methodology/approach
The AMSE roadmap is made of four operating phases – Assessment, Monitoring, Sustainability, Expansion – it is a Model to govern the LSS deployment and to maximize both operative and economical results on a long-term basis.
Findings
One of the main problems of LSS programs is their sustainability (sustainability of projects and the overall program) over time; the AMSE Model allows the deployment of an LSS Governance Structure with a clear definition of tasks; this model can be effectively applied both to small and medium enterprises (SMEs) and global companies, regardless of the sector.
Practical implications
Both SMEs and global corporations could benefit from applying the AMSE in terms of operational efficiency, culture improvement and people engagement.
Originality/value
The AMSE Model represents an innovative approach for sustaining a continuous improvement culture in the organizations over time, by defining four steps (Assessment, Monitoring, Sustainability, Expansion), divided into detailed tasks, each of which is characterized by its own specific tools.
This letter presents a smart driver for LEDs, particularly for automotive lighting applications, which avoid ringing and overshoot phenomena. To this aim, advanced Soft Start and Current Slope Control techniques are integrated on-chip. This letter discusses the driver design integrating in high voltage CMOS technology, the digital circuitry for programming and electronic control units interfacing, and the power devices up to 10 W. Experimental characterizations with LEDs of different power levels and with different types of connections are showed. The smart driver sustains automotive temperature and voltage requirements; moreover it has high power efficiency, it is programmable, and can be configured to work as a linear regulator (for low current LEDs) or in switch mode (for higher power LEDs)
The new FF-LYNX communication protocol, aiming at the fulfillment of non-homogeneous latency and bandwidth requirements of future High Energy Physics experiments, as well as its implementation into IP Cores available for ASICs development, are described in this paper. The first test-chip implementing FF-LYNX IP-Cores has been designed in the IBM 130 nm CMOS technology, adopting radiation hardening techniques. Transmitter and Receiver interfaces, designed in three different speed options, 4 × F, 8 × F and 16 × F (F= reference clock frequency), as well as different rad-hard FIFOs, constitute the overall architecture of the testchip. A detailed analysis of the area, power consumption and speed has been performed besides the functional characterization, by means of a configurable test-bed. X-ray irradiation tests have been carried out at CERN facilities to verify the Total Ionization Dose hardness of the interfaces, with their full functionality up to 40 Mrad( SiO2)
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