Development, Design and Characterization of a Novel Protocol and Interfaces for the Control and Readout of Front-End Electronics in High Energy Physics Experiments

Abstract

The new FF-LYNX communication protocol, aiming at the fulfillment of non-homogeneous latency and bandwidth requirements of future High Energy Physics experiments, as well as its implementation into IP Cores available for ASICs development, are described in this paper. The first test-chip implementing FF-LYNX IP-Cores has been designed in the IBM 130 nm CMOS technology, adopting radiation hardening techniques. Transmitter and Receiver interfaces, designed in three different speed options, 4 × F, 8 × F and 16 × F (F= reference clock frequency), as well as different rad-hard FIFOs, constitute the overall architecture of the testchip. A detailed analysis of the area, power consumption and speed has been performed besides the functional characterization, by means of a configurable test-bed. X-ray irradiation tests have been carried out at CERN facilities to verify the Total Ionization Dose hardness of the interfaces, with their full functionality up to 40 Mrad( SiO2)

A high-speed driver for silicon photonics Mach-Zehnder modulator for high data-rate transfer of particle collision images in high-energy physics and in medical physics

“…"raw" data). These different requirements can be accomplished using different physical links or using protocols that make the sharing of the same link by data that must be transmitted with different priority possible [8]. Different data reduction techniques will be applied to make the transmission of "trigger" data compatible with available link bandwidths.…”

Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

“…Many papers are focused, for example, just on high-level modeling and system verification step such as [10] in which a Simulink-based tool is used. Other works are focused on verification using FPGA-based prototyping platforms [11][12][13][14][15] or mainly on chip testing [16,17] using SystemVerilog. Similar approaches as that explained in this paper are in [18,19] where the design and verification step, for consumer electronics devices, is based on Simulink language.…”

Dynamic reconfiguration in FPAA for technical and nontechnical education in a global environment

“…In this sense, remote laboratories based on dynamic reconfigurations, by means of opening and closing relays and a matrix of nodes, that use discrete analog components are having good results, like Virtual Instrument Systems in Reality (VISIR) [19,41], but even for those initiatives, it is not possible to cover every single possibility due to the broad spectrum of components required in a typical analog electronics practical course. In addition, it is not easy to create complex lab practices, and their design requires alternative approaches to those originally adopted [40]. Another concern is that they are not oriented to be used by nontechnical students.…”